Complexity Challenge Status Erno DAVID Wigner Research Center for Physics (HU) 26 January, 2016

2 Complexity Challenge Status (History) April 2015: First CC design (x24 GBT links, 1920 FIFOs, dual x8 PCIe DMA) The result – The design can be fitted into Arria 10 But this was based on a code base which is now obsolete July 2015 (1 st CRU Workshop): Our new Arria 10 GBT-FPGA port is ready Decision to rebuild the CC design and develop a more accurate “dummy cluster finder” logic with the TPC team November 2015: First release of the new core CRU framework with x24 GBT links, x1 TTS link, x2 PCIe x8, the User Logic part contains just a skeleton (there is no dummy CF inside) January 2016: It become evident that the GBT-FPGA resource usage is not realistic (it is too low)

3 Complexity Challenge Status (Current and Next Steps) Current Steps: We are investigating the issues and working on the solution We have promising results in a standalone projects where the GBT-FPGA resource usage looks more accurate The results will released after integration with the core CRU framework and double checking Next Steps: Fix the x24 version and check the resource usage Extend the design to x48 version and check the resource usage Rebuild the x48 design with GBT-FPGA Rx in Wide Bus mode Apply additional optimizations (like only x10 Tx and x40 Rx) Comments: One of the main design goal of the common CRU framework is to allow parallel work between the core CRU team and the detector teams The core CRU framework is under development (currently there is no GBTx, GBT-SCA, CRU control, TTS, raw GBT payload recorder and PICe DMA aggregator code) Expected in 1–2 weeks Requires more time and depends on the previous results