CHARLES UNIVERSITY IN PRAGUE faculty of mathematics and physics Principles of Computers 19 th Lecture Pavel Ježek, Ph.D.

Address decode 8-bit Sound Card HCI... $F $F DD $F $F $F $F Data W/O reg RWAddr reg PlayAdr reg Playback logic Loudspeaker image (CC Attribution) authored by Sallee Design, DAC auto increment sound buffer (100kB – MB)

Address decode 16-bit Sound Card HCI (Byte Ordering as Part of HCI)... $F DD $F DD $F $F $F $F Data W/O reg MSB LSB RWAddr reg PlayAdr reg Playback logic Loudspeaker image (CC Attribution) authored by Sallee Design, DAC auto increment on MSB write (LSB and MSB must be written at once during a single 16-bit write [if on 16-bit system bus] or LSB must be written first and MSB second if on 8-bit system bus) auto increment sound buffer (100kB – MB)

Address decode 16-bit Sound Card HCI... $F DD $F DD $F AA $F $F $F Data W/O reg MSB LSB RWAddr R/W reg PlayAdr reg Playback logic Loudspeaker image (CC Attribution) authored by Sallee Design, DAC auto increment sound buffer (100kB – MB)

Address decode 16-bit Sound Card HCI... $F DD $F DD $F AA $F CF $F $F Data W/O reg MSB LSB RWAddr R/W reg Config R/W reg ▪sample rate ▪sample size ▪mono/stereo PlayAdr reg Playback logic Loudspeaker image (CC Attribution) authored by Sallee Design, DAC auto increment sound buffer (100kB – MB)

Address decode 16-bit Sound Card HCI... $F DD $F DD $F AA $F CF $F CT $F Data R/W reg MSB LSB RWAddr R/W reg Config R/W reg ▪sample rate ▪sample size ▪mono/stereo Control W/O reg ▪play/stop ▪record/stop PlayAdr reg Playback logic Loudspeaker image (CC Attribution) authored by Sallee Design, DAC auto increment sound buffer (100kB – MB)

Address decode 16-bit Sound Card HCI... $F DD $F DD $F AA $F CF $F CT $F ST... Data R/W reg MSB LSB RWAddr R/W reg Config R/W reg ▪sample rate ▪sample size ▪mono/stereo Control W/O reg ▪play/stop ▪record/stop Status R/O reg ▪play position ▪playing? ▪recording? PlayAdr reg Playback logic Loudspeaker image (CC Attribution) authored by Sallee Design, DAC auto increment sound buffer (100kB – MB) Base address: $F

I 2 C Bus Arbitration Original source: Embedded Systems Academy - Bus Arbitration:

Sending 1 Byte Via Philips PCA9564 I 2 C HBA W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) R I2CCON → wait for SI=1 (controller waits for I2C idle state) R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) R I2CCON → wait for SI=1 R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send R I2CCON → wait for SI=1 R I2CSTA → $28=ACK received → $30=NACK received → $38=arbitration lost W I2CCON ← (STA=0,STO=1) Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O)

Sending 1 Byte Via Philips PCA9564 I 2 C HBA W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) R I2CCON → wait for SI=1 (controller waits for I2C idle state) R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) R I2CCON → wait for SI=1 R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send R I2CCON → wait for SI=1 R I2CSTA → $28=ACK received → $30=NACK received → $38=arbitration lost W I2CCON ← (STA=0,STO=1) Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) If everything is ideal: 1 transaction on I 2 C bus = 11 transactions on system bus (or more, if not ideal)

Sending 1 Byte Using Interrupts procedure SendByte(…); begin set interrupt X handler W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler end; procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler end; procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received → $38=arbitration lost W I2CCON ← (STA=0,STO=1) set interrupt X handler = default end; Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O)

Sending 1 Byte Using Interrupts procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler end; procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler end; procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received → $38=arbitration lost W I2CCON ← (STA=0,STO=1) set interrupt X handler = default end; Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) RACE CONDITION!

Sending 1 Byte Using Interrupts procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler end; procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler end; procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received → $38=arbitration lost W I2CCON ← (STA=0,STO=1) set interrupt X handler = default end; Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) RACE CONDITION! If interrupt arrives here, we will send the same data byte for the second time!

Sending 1 Byte Using Interrupts procedure SendByte(…); begin set interrupt X handler W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) set interrupt X handler W I2CDAT ← (slave addr|R/W=0=write) end; procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost set interrupt X handler W I2CDAT ← data byte to send end; procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received → $38=arbitration lost set interrupt X handler = default W I2CCON ← (STA=0,STO=1) end; Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O)

PIO (Programmed I/O) 6502: LDA ctrl_data_reg_address STA buffer_address

PIO (Programmed I/O) 6502: LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx

PIO (Programmed I/O) 6502: LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx 6502: LDA addr = 3 byte instruction STA addr = 3 byte instruction 3 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 3 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 8 tx

PIO (Programmed I/O) 6502: LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx 6502: LDA addr = 3 byte instruction STA addr = 3 byte instruction 3 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 3 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 8 tx e.g. system bus: 1 byte/tx 2 cycles/tx 1 MHZ cycles = 0,5 MB/second = x B/s PIO transfer = (x / 8) B/s = 62,5 kB/s

PIO (Programmed I/O) 6502: LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx 6502: LDA addr = 3 byte instruction STA addr = 3 byte instruction 3 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 3 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 8 tx e.g. system bus: 1 byte/tx 2 cycles/tx 1 MHZ cycles = 0,5 MB/second = x B/s PIO transfer = (x / 8) B/s = 62,5 kB/s Solution: DMA