Data Acquisition System for NPDGamma Nadia Fomin April 4 th, 2008 Bon Appetit!

VME 1VME 2VME 3HAZEL/DAQ CLOVER/CONTROL DAQ! You SSH

4 rings – 12 Cesium Iodide detectors each Detector Signal - S j i Instead of storing the signal from each detector for every neutron pulse:  => Average signal for a ring =4 SUM Signals=>VME3  S diff,i j => S i j - => 48 DIFFERENCE Signals => VME2  100 time bins for SUM and DIFFERENCE signals, with each time bin summed over 20 (DIFFs) and 25 (SUMS) samples (1 ≤ i ≤ 12) (1 ≤ j ≤ 4)

4 rings – 12 Cesium Iodide detectors each Detector Signal - S j i Instead of storing the signal from each detector for every neutron pulse:  => Average signal for a ring =4 SUM Signals=>VME3  S diff,i j => S i j - => 48 DIFFERENCE Signals => VME2  100 time bins for SUM and DIFFERENCE signals, with each time bin summed over 20 (DIFFs) and 25 (SUMS) samples (1 ≤ i ≤ 12) (1 ≤ j ≤ 4)

VME 1VME 2VME 3 Difference SignalsProton Current Sum Signals RFSF Voltage and Current Monitor Data (3) => Data from each pulse is written to 3 files, corresponding to the VME that it came from. => Data from each pulse is preceded by a header (in each of the 3 files), including:  Date and time  Time (us) since last pulse (better be 50ms)  Pulse number  DIO data -> most meaningful in VME3, which records the spin sequence  Time since last data write and number of records written

TTL N C C N VME 1.4 Alphi Scanclock FIFO TO TTL VME 1.3 DIO Pins 4 TTL delay b VME 1.? Joerger gate FIFO 4.1 ab Clock out Pins 2 b a Fiberoptic Link Receiver VME 2 ?a NIM Gate/Delay Generator 1us

c VME 1.7 Joerger WF GEN nim TTL a b N N C VME FIFO 2.3 NIM 3.1 Gate/Delay Generator 3.2 Gate/Delay Generator fold Logic Gate 4 Gate/Delay Generator T0 Copy to VME2 VME 1.4 Alphi VME 1.3 DIO VME 1.8 Joerger 2 Scanclock 8 gate d b a c d A B out trigger reset Gate ff AB 4 trigger ttl 6 c RESET 12 Clock out 14 | 17 Spin Seq Out delay RFSF T0 T c a SF out b b Gate 80 ns Note: Wire on right T0 TTL

VME 1.5 LeCroy 1182 VME 1 VME 1.3 DIO Pins 14 Pins 2 Joerger Scalar TTL N C C N b NIM In - ? Arm In FIFO 3.1 FIFO 3.2 FIFO COINC 2.2 COINC FIFO Gate/Delay Generator 6.2 Gate/Delay Generator 6.3 Gate/Delay Generator 6.4 Gate/Delay Generator FIFO 5.1 FIFO 5.2 FIFO 5.3 FIFO Gate/Delay Generator 4.2 Gate/Delay Generator TTL 8.1 Gate/Delay Generator 8.2 Gate/Delay Generator A 8 us 10.1 COINC 7.2 COINC 9.1 Gate/Delay Generator 9.2 Gate/Delay Generator COINC Hz Ref nim Digital Delay Pulse Generator ttl Ext. Trig 1 us delay T0 1 us - wide a a VME 1.6 LeCroy a aa b bb TTL Gate – 1us a RFSF T0 Gated T0 3 b Out – 10 ns wide 2 b b

Current Status:  After some changes, VME1 and VME3 take data (huge improvement from last week when none worked)  VME2 is not completely operational (takes data even when T0 cable is unplugged)  Once it’s up and running, a noise measurement will be done, and then work on the 60hz “upgrade” will seriously begin SNS – 60 Hz operation Doing the naïve software switch, and scaling 20Hz->60Hz, VME2 (largest volume of data) can’t keep up. Issue -> DMA transfer, ADCs can’t read/write simultaneously

1.Figure out the minimum amt of time that VME2 needs to read out the ADCs, see if that can be found during the SNS pulse. Problem: All neutrons are slow and probably useful. Upside: If enough time, no money or significant coding/procedural changes. 2.Add more memory to the ADCs, so that 8 pulses can be stored (one octet), read out every 9th pulse. Problem: Costs money. Upside: Lose few good pulses. BUT! SNS pulses are shorter, so 8 might already fit! 3. Possibly alter the spin sequence, so that every nth (3rd?) sequence is garbage and use that time for data transfer. So, we'd still have an octet, but it would be a subset of 12 spin sequences. Problem: Throw away a third of good pulses. Example: (1,0,0,1,0,1,1,0)-> (1,0,X,0,1,X,0,1,X,1,0,X) 4. Installing a real-time kernel. Not sure how that'll fix the problem. Ideas :