EEE2243 Digital System Design Chapter 7: RTL Design by Muhazam Mustapha, March 2011

Learning Outcome By the end of this chapter, students are expected to understand the principle of RTL design

Chapter Content Principle of RTL Design Example (Soda / Soft Drink Dispenser) Verilog Modular Coding

RTL Design

RTL stands for “Register Transfer Level” RTL design is the level of digital system design that involves the datapath components and the routing of the data (information) between the components with an addition of a CENTRALIZED controller In this chapter we will see the general steps that involves in RTL design

Steps

Soda Dispenser Example

Examples from text book The Vahid’s text book provides many examples for you to study It is up to you read them as we won’t have enough time to cover all examples We will only discuss the soda dispenser example from the text book

Soda Dispenser Problem Specification: c: bit input, 1 when coin deposited a: 8-bit input having value of deposited coin s: 8-bit input having cost of a soda d: bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda as c d Soda dispenser processor tot: 25 tot: 50 as c d Soda dispenser processor

Soda Dispenser: Step 1 Capture High Level State Machine: Declare local register tot Init state: Set d=0, tot=0 Wait state: wait for coin –If see coin, go to Add state Add state: Update total value: tot = tot + a –Remember, a is present coin’s value –Go back to Wait state In Wait state, if tot >= s, go to Disp(ense) state Disp state: Set d=1 (dispense soda) –Return to Init state Wait Add Disp Init d=0 tot=0 c’*(tot<s) d=1 c tot=tot+a

Soda Dispenser: Step 2 Create Datapath: Need tot register Need 8-bit comparator to compare s and tot Need 8-bit adder to perform tot = tot + a Wire the components as needed for above Create control input/outputs, give them names ld clr tot 8-bit < adder sa Datapath tot_ld tot_clr tot_lt_s

Soda Dispenser: Step 3 Connect Datapath to a Controller: Controller’s inputs –External input c (coin detected) –Input from datapath comparator’s output, which we named tot_lt_s Controller’s outputs –External output d (dispense soda) –Outputs to datapath to load and clear the tot register tot_lt_s tot_clr tot_ld ControllerDatapath s c d a 88

Soda Dispenser: Step 4 Derive the Controller’s FSM: Same states and architectures as high- level state machine But set/read datapath control signals for all datapath operations and conditions using the state and input values Inputs::c,tot_lt_s (bit) Outputs:d,tot_ld,tot_clr (bit) Wait Disp Init d=0 tot_clr=1 c’* tot_lt_s’ c’ * tot_lt_s d=1 c tot_ld=1 c d tot_ld tot_clr tot_lt_s Controller Add ld clr tpt 8-bit < adder sa Datapath tot_ld tot_clr tot_lt_s tot_clr tot_ld Controller Datapath s c d a 88

Soda Dispenser: Completing the design: Implement the FSM as a state register and logic

Verilog Modular Coding

Modular Coding So far we have done Boolean algebra and behavioral style of Verilog coding There is a third style in the coding i.e. the modular style Modular means we split the code into more than one files In Quartus II, at certain stage in the project creation, we need to specify the modules involve in the project These modules will then be callable from a main module

Modular Adder module addbit(a, b, ci, sum, co); input a; input b; input ci; output sum; output co; wire a; wire b; wire ci; wire sum; wire co; assign {co,sum} = a + b + ci; endmodule module adder4(result, carry, r1, r2, ci); input [3:0] r1, [3:0] r2, ci; output [3:0] result, carry; wire [3:0] r1, [3:0] r2, ci, [3:0] result, carry; wire c1, c2, c3; addbit u0 (r1[0], r2[0], ci, result[0], c1); addbit u1 (r1[1], r2[1], c1, result[1], c2); addbit u2 (r1[2], r2[2], c2, result[2], c3); addbit u3 (r1[3], r2[3], c3, result[3], carry); endmodule

Modular Adder module addbit(a, b, ci, sum, co); input a; input b; input ci; output sum; output co; wire a; wire b; wire ci; wire sum; wire co; assign {co,sum} = a + b + ci; endmodule module adder4(result, carry, r1, r2, ci); input [3:0] r1, [3:0] r2, ci; output [3:0] result, carry; wire [3:0] r1, [3:0] r2, ci, [3:0] result, carry; wire c1, c2, c3; addbit u0 (.a (r1[0]),.b (r2[0]),.ci (ci),.sum (result[0]),.co (c1)); addbit u1 (.a (r1[1]),.b (r2[1]),.ci (c1),.sum (result[1]),.co (c2)); addbit u2 (.a (r1[2]),.b (r2[2]),.ci (c2),.sum (result[2]),.co (c3)); addbit u3 (.a (r1[3]),.b (r2[3]),.ci (c3),.sum (result[3]),.co (carry)); endmodule