Combinational Logic Logic gates. and, or, not Derived gates. nand, nor, xor John F. Wakerly – Digital Design. 4 th edition. Chapter 4.

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Combinational Logic Logic gates. and, or, not Derived gates. nand, nor, xor John F. Wakerly – Digital Design. 4 th edition. Chapter 4.

Logical design

 Electronic circuits which combine digital signals according to the Boolean algebra are referred to as logic gates  Gates - because they control the flow of information. Logic gates There is no limit to the number of inputs that may be applied to a function, so there is no functional limit to the number of inputs a gate may have. However, for practical reasons, commercial gates are most commonly manufactured with limited inputs (2, 3, or 4 ). In digital circuits all inputs must be connected. &

The AND gate The AND gate implements the AND function. With the gate shown to the left, both inputs must have logic 1 signals applied to them in order for the output to be a logic 1. &

 The OR function, like its verbal counterpart, allows the output to be true (logic 1) if any one or more of its inputs are true. The OR gate 1

 Besides implementing of the logical AND, OR functions the above mentioned devices have also “gate” functions.  With each of these devices the “gate” function works differently  There is a status of the gate - OPEN or CLOSE.  When the gate is OPEN then the logical value of the input (signal) can pass to the output of the gate.  When the gate is Closed then the logical value of the input (signal) can not pass to the output of the gate. How the gates work ? A B Z Closed A B B Opened

 To force the device to work as a gate we have to satisfy the input conditions.  For the AND gate the logical value 1 of one of the inputs of the gate allows the other input’s value to pass to the output.  The output of the AND gate will be always 0 if one of the inputs we keep = 0.  The input which we intentionally keep in 0 or 1 condition we call the control input.  The other input which is passed or not to the output we call the data input. Control and data input. AND 0 B 0 Closed & Conrol Input Data Input Opened Conrol Input Data Input Opened Conrol Input Data Input & &

 For the OR gate the control input should be 0 to allow the data input to pass to the output (Opened).  If we keep the control input =1 then the OR gate will be closed keeping the output value stable 1. OR gate 1 B 1 Closed 1 Conrol Input Data Input Opened Conrol Input Data Input Opened Conrol Input Data Input 1 1

 The inverter has exactly one input as well as one output.  Whatever logical state is applied to the input, the opposite state will appear at the output.  The circle at the output of the NOT gate denotes the logical inversion Inverter

 The three basic functions AND, OR, and NOT are sufficient to accomplish all possible logical functions and operations  Some combinations are used so commonly that they have been given names and logic symbols of their own: NAND, NOR, XOR. Derived Logical Functions and Gates The NAND Gate & The circle at the output of the NAND gate denotes the logical inversion, just as it did at the output of the inverter.

 The NOR gate is an OR gate with the output inverted. The NOR Gate 1

 The XOR gate produces a logic 1 output only if its two inputs are different.  If the inputs are the same, the output is a logic 0  It’s comparator The Exclusive-OR, or XOR Gate  different 1  equal 0 A B B A

 Logic circuits are classified into two types, “combinational” and “sequential.”  A combinational logic circuit is one whose outputs depend only on its current inputs.  Sequential circuits are designed to actually remember the past states of their inputs, and to produce outputs based on those past signals as well as the current states of their inputs.  These circuits can act in accordance with a sequence of input signals, and are therefore known as sequential logic circuits. Combinational and sequential logic circuits. combinational logic circuits – don’t have memory, are very fast sequential logic circuits- have memory, are slow

Typical Hardware Design Flow