-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B. Kahng ‡† and Mulong Luo † Presented By: Siddhartha Nath

-2- Outline Introduction and Related Works Introduction and Related Works Crosstalk-Aware Layout Optimization Crosstalk-Aware Layout Optimization Testcase Generation Testcase Generation Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-3- Introduction DRAM interconnect channels DRAM interconnect channels –Narrow and long interconnect channel  large crosstalk  large crosstalk –Manual design is still the dominant methodology  might be far from optimal … Aggressor Victim An automated DRAM channel layout optimizer is essential to minimize the crosstalk effects

-4- Related Works Crosstalk-aware analysis Crosstalk-aware analysis –Analytical modeling of crosstalk-induced delay and noise [Xiao00] –Arrival time alignment of aggressor and victim for worst- case victim delay and noise [Gross98, Sato00] Crosstalk-aware design Crosstalk-aware design –Swizzling-based interconnect design to reduce crosstalk-induced delay and noise [Yu09] –Crosstalk-aware MILP-based detailed routing [Gao93] No existing works integrate accurate crosstalk-aware analysis and automated design!

-5- Our Contributions Develop an accurate closed-form analytical delay calculator Develop an accurate closed-form analytical delay calculator Propose several methods to achieve high- quality, scalable channel layout optimization Propose several methods to achieve high- quality, scalable channel layout optimization –MILP-based segment optimization –Pair-swapping segment optimization Achieve 29% reduction of maximum weighted delay uncertainty compared to the conventional signal permutation Achieve 29% reduction of maximum weighted delay uncertainty compared to the conventional signal permutation

-6- Outline Introduction and Related Works Introduction and Related Works Crosstalk-Aware Layout Optimization Crosstalk-Aware Layout Optimization Testcase Generation Testcase Generation Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-7- Track 1 Track 2 Track 3 Track 4 Segment 1 Segment 2 Segment 3 Segment 4 Segment |G| … Track |T| … … Problem Statement Inputs: Inputs: –Long and narrow rectangular channel  set of tracks T –Set of segments G; set of signals S –Criticality classes (e.g., CLK signal  highest criticality) –Design rules (e.g., pitch, width, spacing) for each class –Inter-buffer length for each class Objective: minimize max weighted delay uncertainty among all signals in different classes Objective: minimize max weighted delay uncertainty among all signals in different classes

-8- Problem Complexity Track t 0 Track t 1 Track t 2 Track t 3 Track t 4 Track t |T|-1 … … ……… Segment g 0 Segment g 1 Segment g 2 Segment g 3

-9- Segment-by-segment Optimization Optimal Max delay uncertainty: 7.16ps Segment-by-segment Max delay uncertainty: 7.19ps Signal permutation Max delay uncertainty: 9.57ps

-10- Overview of Crosstalk-Aware Layout Optimization Testcase specifications: channel length and width, #signals, #tracks, etc Testcase specifications: channel length and width, #signals, #tracks, etc Segment-by-segment optimization Segment-by-segment optimization –MILP-based segment optimization –Pair-swapping segment optimization Accurate and fast delay uncertainty calculator Accurate and fast delay uncertainty calculator Pair-swapping segment optimization MILP-based segment optimization Optimized layout with min delay uncertainties of signals Testcase specifications Segment-by-segment optimization Delay Uncertainty Calculator

-11- MILP-based Segment Optimization: Notations

-12- Basic Constraints for Our MILP

-13- Track t 0 Track t 1 Track t 2 Track t 3 Track t 4 Track t |T|-1 … … … Segment g j Segment g j+1 MILP-based Segment Optimization Signal 1 Signal 2 Signal 3 Signal 4

-14- Decomposition for Scalability Limitation of MILP-based method  scalability Limitation of MILP-based method  scalability –Decompose tracks into set of subsets –Solve MILP instance for each subset –Offset half of the subset size to mix signals Track t 1 Track t 2 Track t 3 Track t |T|-1 … … ……… Segment g 0 Segment g 1 Segment g 2 Segment g 3 |V 0 |=V |V 1 |=V |V 2 |=V|V 3 |=V|V 1 |=V|V 2 |=V|V 3 |=V |V 0 |=[V/2] |V 0 |=V |V 1 |=V |V 2 |=V|V 3 |=V|V 1 |=V|V 2 |=V|V 3 |=V |V 0 |=[V/2]

-15- Overview of Crosstalk-Aware Layout Optimization Testcase specifications: channel length and width, #signals, #tracks, etc Testcase specifications: channel length and width, #signals, #tracks, etc Segment-by-segment optimization Segment-by-segment optimization –MILP-based segment optimization –Pair-swapping segment optimization Accurate and fast delay uncertainty calculator Accurate and fast delay uncertainty calculator Pair-swapping segment optimization MILP-based segment optimization Optimized layout with min delay uncertainties of signals Testcase specifications Segment-by-segment optimization Delay Uncertainty Calculator

-16- Pair-swapping Segment Optimization Main idea: swap the signal with maximum weighted delay uncertainty with other signals Main idea: swap the signal with maximum weighted delay uncertainty with other signals Procedure: Procedure: Step1: Sort all the signals in increasing order of delay uncertainties Step2: Swap the signal w/ max weighted delay uncertainty and min weighted delay uncertainty Step 3: Revert the swap if no improvement Step 4: Repeat Steps 1, 2 until no weighted delay uncertainty improvement 70ps 30ps Track t 1 Track t 2 Track t 3 Segment g 1 Segment g 2 40ps 45ps 60ps

-17- Overview of Crosstalk-Aware Layout Optimization Testcase specifications: channel length and width, #signals, #tracks, etc Testcase specifications: channel length and width, #signals, #tracks, etc Segment-by-segment optimization Segment-by-segment optimization –MILP-based segment optimization –Pair-swapping segment optimization Accurate and fast delay uncertainty calculator Accurate and fast delay uncertainty calculator Pair-swapping segment optimization MILP-based segment optimization Optimized layout with min delay uncertainties of signals Testcase specifications Segment-by-segment optimization Delay Uncertainty Calculator

-18- Delay Uncertainty Calculator Layout and electrical information of any aggressors and victims Noise waveform to Delay Change Curve (DCC) [Sato03] Delay Calculator Delay uncertainty induced by crosstalk

-19- Accuracy of Delay Uncertainty Model Comparison of our model and the model in [Gupta04] Comparison of our model and the model in [Gupta04] –Testcase: five signals, five tracks and 8000um channel divided into 8 segments –Randomly generate 300 swizzling patterns  1500 data points –Rank correlation between our model and SPICE –Rank correlation between [Gupta04] model and SPICE [Gupta04] P. Gupta and A. B. Kahng, “Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling”, Proc. VLSI Design, 2004, pp Rank of delay uncertainty by our model Rank of delay uncertainty by SPICE Max rank difference: 148 Rank of delay uncertainty by [Gupta04] Rank of delay uncertainty by SPICE Max rank difference: 487

-20- Outline Introduction and Related Works Introduction and Related Works Crosstalk-Aware Layout Optimization Crosstalk-Aware Layout Optimization Testcase Generation Testcase Generation Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-21- Testcase Generation: General Inputs No public benchmark for DRAM channel routing optimization  develop testcase generator No public benchmark for DRAM channel routing optimization  develop testcase generator General inputs General inputs –Channel length –Channel width –Number of signals –Number of tracks –Number of segments –Probability that a signal in class 0 is correlated with a signal in class 1 –Supply voltage –Clock period class 0class 1class 2class 3class 4 class class class class class 40.5 … Channel length Channel width Signals Tracks Segment

-22- Testcase Generation: More Inputs Class-specific inputs Class-specific inputs Number of signals Number of signals Ground capacitance (Resistance) Ground capacitance (Resistance) Coupling capacitance between two signals in different classes Coupling capacitance between two signals in different classes Distances between any two consecutive buffers Distances between any two consecutive buffers Input capacitance (Output resistance) of buffer Input capacitance (Output resistance) of buffer Signal-specific inputs Signal-specific inputs Load capacitance Load capacitance Input resistance Input resistance Input slew Input slew Activity correlation with other signals Activity correlation with other signals Load cap. Input resistance Input slew Input cap. Output res. Distance Signal 1

-23- Outline Introduction and Related Works Introduction and Related Works Crosstalk-Aware Layout Optimization Crosstalk-Aware Layout Optimization Testcase Generation Testcase Generation Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-24- Experimental Setup Channel length = 8000um Channel length = 8000um Pitch, width, space and buffer location of each class Pitch, width, space and buffer location of each class Signal-specific inputs: R d = 500Ω, t slew = 130ps, C load = 4fF Signal-specific inputs: R d = 500Ω, t slew = 130ps, C load = 4fF Experiment 1: Impact of number of signals and tracks Experiment 1: Impact of number of signals and tracks Experiment 2: Impact of percentage of signals in each class Experiment 2: Impact of percentage of signals in each class Experiment 3: Impact of correlation of signals Experiment 3: Impact of correlation of signals Experiment 4: MILP vs. pair-swapping vs. signal permutation Experiment 4: MILP vs. pair-swapping vs. signal permutation ClassPitch (um)Width (um)Space (um)Buffer location Per 1000um Per 1000um Per 2000um Per 4000um No buffer

-25- Experiment 1: Impact of Number of Signals and Tracks Vary number of tracks and signals Vary number of tracks and signals Weights of classes = {10, 6.7, 4, 2, 1} Weights of classes = {10, 6.7, 4, 2, 1} Same number of signals in each class Same number of signals in each class Testcase E1T1 result Testcase E1T1 result –Signals in higher-criticality class  smaller delay uncertainty –Most critical two signals  mostly on the boundary of channel Testcase#signals#tracks E1T1 10 E1T E1T E1T4 20 E1T E1T Class 0 Class 2 Class 3 Class 4 Class 1

-26- Experiment 2: Impact of Percentage of Signals in Each Class Number of tracks = 20 and Number of signals = 20 Number of tracks = 20 and Number of signals = 20 Change the percentage of signals in each criticality class Change the percentage of signals in each criticality class Same weights used in Experiment 1 Same weights used in Experiment 1 Observation Observation –% of lower-criticality signals ↑  objective ↓ –Replace higher-criticality signals to lower-criticality signals  maximum weighted delay uncertainty ↓ Test case Priority of class A Priority of class B #signals in class A #signals in class B D max A D max B Objective E2T E2T E2T E2T E2T E2T

-27- Experiment 3: Impact of Correlation of Signals Layout of channel for E3T1 Layout of channel for E3T2

-28- Max weighted delay uncertainty for testcases T2 – T5 Runtime of MILP and pair-swapping for testcases T2 – T5 MILP vs. Pair-Swapping vs. Signal Permutation (2) Scalability evaluation with larger testcases Scalability evaluation with larger testcases Size of decomposition subset of MILP: 20 Size of decomposition subset of MILP: 20 Testcases T2 – T5 Testcases T2 – T5 –T2: #tracks = 100, #signals for each class = {15, 40, 30, 10, 5} –T3: #tracks = 110, #signals for each class = {15, 40, 30, 10, 5} –T4: #tracks = 200, #signals for each class = {30, 80, 60, 20, 10} –T5: #tracks = 220, #signals for each class = {30, 80, 60, 20, 10} Observation Observation –Pair-swapping achieves better results than signal permutation  Up to 29% max weighted delay uncertainty reduction  Up to 29% max weighted delay uncertainty reduction –Empty tracks (10% of #tracks)  Up to 19.9% max weighted delay uncertainty reduction –Runtime: pair-swapping < MILP 19.9% 29%

-29- Outline Introduction and Related Works Introduction and Related Works Crosstalk-Aware Layout Optimization Crosstalk-Aware Layout Optimization Testcase Generation Testcase Generation Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-30- Conclusions Propose a DRAM routing channel optimization to specifically target the layout design of long, resource- constrained channels in modern DRAM products Propose a DRAM routing channel optimization to specifically target the layout design of long, resource- constrained channels in modern DRAM products Optimizer is signal criticality-aware, and minimizes a maximum weighted delay uncertainty Optimizer is signal criticality-aware, and minimizes a maximum weighted delay uncertainty Achieve up to 29% reduction of maximum weighted delay uncertainty compared to a traditional track permutation methodology Achieve up to 29% reduction of maximum weighted delay uncertainty compared to a traditional track permutation methodology Ongoing work Ongoing work –Flexible buffer location –Use of inverters

-31- Acknowledgments Work supported by Samsung Electronics

-32- Thank You!