2004 Multichannel integrated circuits for digital X-ray imaging with energy windowing Krzysztof Świentek Department of Nuclear Electronics FPNT, AGH Kraków

2004 Introduction – multichannel ASICs Noise in MOS transistors Crosstalk in mixed–mode integrated circuits Random matching RX64DTH – digital imaging using silicon detectors Measurements results – chip tutorial Summary Content

2004 Introduction  multichannel ASIC Input signals - small amplitude (Qin = 1400 el) - stochastic character (amplitude, time) SET OF SENSORS ( silicon strip detector) MULTICHANNEL INTEGRATED CIRCUITS (analogue & digital blocks) CROSSTALK digital  analogue LIMITS: power & area LOW LEVEL OF NOISE UNIFORMITY OF PARAMETERS 6.5 mm RX64DTH

2004 Noise in MOS transistors saturationlinear Simulations (HSPICE) NLEV=3 BSIM3v3 (NIMOD=2) 1. Thermal noise of channel Measurments – short channel effects (2-10x): ( velocity saturation, hot electrons) 2. Flicker noise Simulations (HSPICE) NLEV=2, 3 Measurments – short channel effects ( hot electrons, RST noise) BSIM3v3 (NIMOD=2)

2004 CROSSTALK Transfer: – common supply lines: parasitic inductance and resistance (V ind =LdI/dt) – common substrate: (substrate  epi, V T =f(V SB ), g mb ) Effects for analogue blocks: switching noise, oscillation etc. Minimisation: – reducing the noise generation, – increasing the immunity of analogue part, – isolation techniques. GENERATION TRANSFER EFFECT DIGITAL BLOCKS ANALOG BLOCKS SILICON SUBSTRATE

2004 RANDOM MATCHING MATCHING - identically design devices have different parameters  P=P 1 -P 2 (  P/P) For MOS transistors: V T0, ,  CMOS 0.7  m -  (V T0 ) NMOS PMOS W/L=2  m/0.7  m 9.72 mV mV W/L=1500  m/1.5  m 0.31 mV 0.63 mV L W L W D Number of cases  P/P [%]

Matching  bias condition differences:  V T, ,  R 4. Symmetry in layout – bias, temperature, orientation, – common centroid geometry, unit cells, – surrounding, metal coverage 2. Reduce sensitivity - proper configuration (Kv  Ci/Cj) 3. Monte-Carlo analysis using HSPICE (matching data for given technology) a) b)

2004 data, control Silicon strip detector Integrated circuit PC computer 100  m current pulses X-rays Signal 10x smaller Stochastic High Energy Physics Key system issues : – fully parallel signal processing for all channels. – only binary information (yes/no) is extracted from each strip. – data from each channel must be stored in the local buffer for the whole measurement period. X-ray imaging using silicon strip detectors

2004 RX64DTH - fully integrated 64-channel chip (CMOS 0.8  m process ) RX64DTH consists of: –64 front-end channels (preamplifier, shaper, two discriminators) –128 pseudo-random counters (20-bit) –internal DACs: two 8-bit threshold setting and and three 5-bit for bias –internal calibration circuit (square wave 1mV-30 mV) –control logic –I/O circuit (interface to external bus) 3700  6500  m 2

2004 Single analogue channel Key design issues: – low noise (ENC  200 el. rms, sensor ) – low power (3-5 mW/channel) – relatively fast shaping (Tp = 0.5  1  s) – uniformity from channel to channel (gain, offset, noise) – immunity to switching noise 0 1 t V t V Preamplifier Shaper Discriminators  C2 C5 C3 t V TpTp V T-HIGH V T-LOW 0

2004 Preamplifier & shaper 1. POWER 2. PEAKING TIME 3. SENSOR 4. PSRR, stability, matching. LIMITATIONS SENSOR: C det I det R bias t V TpTp Minimum of noise (transistor dimensions, bias) Hand calculation Simulation HSPICE Other transistors Measurements (bias, temp., Tp) M1: 500/1 M5: 2/120 M4: 100/10 Id = 500  A t V DAC currents – IFED – IFEDSH – ICAS

2004 ENCversus Peaking Time ENC – total noise ENC W – white voltage noise ENC f – 1/f voltage noise ENC i – white current noise t V TpTp Noise types T P [  s] Peaking time T P Optimal  the lowest noise Fast Front-end  increasing noise

2004 Discriminator – offsets, crosstalk AC coupling differential stage (CMRR) hysteresis power supply lines, guard rings 0 1 t V TpTp V T-HIGH V T-LOW 0 1

2004 Pseudo-random counters – 20 bit counters (large dynamic range of the image) – small layout area (only 8 transistor per bit) – 128 counters are grouped in the 8 blocks of 16 counters each (8 bit I/O bus to minimize the dead time)

2004 I/O circuits: LVDS standard (command, clock) 8-bit data bus (tristate), 3-bit address (up to 8 chips) Functionality & testability Calibration circuits: Q inj =Ct  V cal (  500 el el) Internal DACs: threshold setting, gain, peaking time 2 x threshold 8-bit 3 x bias 5-bit 1 x calibration 4-bit 6 dacs Command codeAction 000SetGateStatus 001ReadoutDestructive 010ReadoutNonDestructive 011CalibrationPulseLong 100CalibrationPulseShort 101CounterPulse 110LoadDac 111Unused code

2004 LAYOUT - floor plan, bias lines, pads Isolation techniques – reduce inductance (separate bias line,pads), – floor plan, bias lines – keep “clean” substrate – LVDS – RC filters – guard rings, shielding 10 9 Floor plan – preamplifier & shaper – discriminators – counters & IOs – digital outputs – control logic – calibration – bias DACs Digital guard ring Digital ground Analog guard ring Analog ground Middle ring

2004 Difference [mV] Difference [LSB] Dac value [LSB] Silicon: 3,67eV/el Window – threshold DAC’s Dac value [LSB] – two independent DACs – common centroid matrix – mixed matrices – matching problem – need software correction Difference between DAC HIGH and LOW 7 LSB

2004 IFED [LSB] IFED SH [LSB] ICAS [LSB] Temp.Gain [  V/el] (  ) Offset [mV] (  ) ENC [el. rms] 8 keV ENC [el. rms] 20 keV ENC [el. rms] Cal room57.63 (0.34) (1.91) 248 (6.1) 232 (7.7) 232 (24) 32 room56.79 (0.34) (1.91) 251 (6.1) 234 (8.5) 32 40room219 (24) 32 48room56.30 (0.37) (1.96) 233 (7.5) 217 (7.3) 213 (15) 32 56room203 (13) ° ° ° °163 Noise versus ICAS & Temp Source Pu238 + Cu Vdet = 130 V Vdd = 4.0 V Vddd = 4.0 V Peltier element for temp. Controled Temp. VTH = 255 VTL = scan VTH = scan VTL = 255

2004 IFED [LSB] IFEDSH [LSB] ICAS [LSB] Temp.Gain [  V/el] (  ) Offset [mV] (  ) ENC [el. rms] 8 keV ENC [el. rms] 20 keV °54.86 (0.39) (1.33) (5.1) (16.7) °54.85 (0.44) (1.09) (6.6) (8.22) °54.86 (0.45) (1.26) (8.5) (9.47) °54.84 (0.49) (1.30) (9.2) (9.46) Noise versus IFED – gain & offset const – window is 5 LSB – Peltier element pin-holes in detector  leakeage current  fast noise increasing } dead channels because out of operating point rescue increase IFED but...

2004 Simulation: T P & Gain as a function of IFEDSH shaper output  TPTP Impulse height T P = 0.7 – 1  s Impulse fall ends  4  s  200 kHz

2004 IFED [LSB] IFEDSH [LSB] ICAS [LSB] Temp.Gain [  V/el] (  ) Offset [mV] (  ) ENC [el. rms] 20 keV °80.54 (0.57) -0.8 (0.9) (4.91) °63.74 (0.52) (1.11) (8.69) °54.85 (0.44) (1.09) (8.22) °50.2 (0.36) (1.24) (9.42) °47.64 (0.35) (1.39) (8.92) °45.52 (0.32) (1.22) (9.36) Gain, Offset & Noise versus IFEDSH – window is 5 LSB – Peltier element min (fast) max (slow) TPTP peaking time

Multichannel mix-mode ASIC : — critical parameters connected together — looking for a golden solution 2.Software corrections : — DACs problem — differences between the chips 3.Noise controling : IFED – better detector  lower noise ICAS – the highier the beter (cooling ?) IFEDSH– high gain gives low noise and speed 4.To do – measurements — speed — uniformity in 6-chip module Summary