TELL1 Ethernet Receiver Vincenzo Bonaiuto Fausto Sargeni Luca Cesaroni Electronic Engineering Department University of Rome “Tor Vergata”

Ethernet Receiver Connection Scheme 6 Gigabit Ethernet links each mezzanine Up to 24 Ethernet links each TELL1

TELL1 Mezzanine Block Scheme

Altera® Triple Speed Ethernet MegaCore ® Function  IEEE Standard compliant  10/100/1000 Mbps Ethernet MAC in half-duplex and full-duplex modes.  Multi-channel MAC – Supports up to 24 ports in MAC only configurations and configurations that implement LVDS I/O; 20 ports in configurations that implement gigabit transceiver blocks.  FIFO-less MAC – Option to exclude internal FIFOs for low-latency system.  Virtual local area network (VLAN) and stacked VLAN tagged frames support as specified by IEEE 802.IQ.  Easy-to-use MegaWizard® interface.  IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators.  Support for OpenCore Plus evaluation.

data_out Receiver FPGA Block Scheme data_in data_err Altera MAC Core Altera MAC Core Write to FIFO Control State Machine Dual Clock Fifo Show Ahead Dual Clock Fifo Show Ahead Ethernet Monitor State Machine Ethernet Monitor State Machine File Register Status Register FPGA: Altera Stratix II sop eop rd addr rd en wr addr wreq wrfull wr en 16 statusword rdreq rdempty data data_val One Ethernet link

Data IN  12 bits: Maximum Energy  5 bits:Maximum Position  12 bits: LSB Timestamp (about 40 MHz)  7 bits:Fine Time  15 bits:Sum of the energy near the maximum (center ±3)  8 bits:CRC  12 bits: Maximum Energy  5 bits:Maximum Position  12 bits: LSB Timestamp (about 40 MHz)  7 bits:Fine Time  15 bits:Sum of the energy near the maximum (center ±3)  8 bits:CRC  20 bits: MSBs Timestamp  8 bits: CRC (of the timestamp):  31 bits: Monitoring (# reconstructed clusters, etc.):  20 bits: MSBs Timestamp  8 bits: CRC (of the timestamp):  31 bits: Monitoring (# reconstructed clusters, etc.): Cluster Packet Synchronizing & Monitoring Packet

Mezzanine-TELL1 FIFO Output Cluster Packet Synchronizing & Monitoring Packet

Error Managment ERROR CODEERRORWRONG PACKET 0 NO ERROR TYPE1 - TYPE2 - 1HEADER ERRORHEADER 0 2TYPE ERRORHEADER 0 3PACKET ERROR TYPE1 1 2 TYPE CRC ERROR TYPE1 - TYPE2 - 5 UNEXPECTED END ERROR HEADER 0 TYPE1 1 2 TYPE FRAME ERROR- -

FPGA 1 st Fitting ALTERA Stratix II - EP2S60F672C3

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Ethernet Frame