Page 62 in Chassaing

The.start directive links the section name to start at location address. For the section to have a valid starting address, the.start statement for the section must precede the.text,.data, or.sect directive that defines the section name..start directive defines the section defines the starting address of the section So the program (text) starts at location and the the data starts at location 809c00.

809c00 809c01 809c02 809c03 809c04 809c05 PBASE STEPSP ATABLE AICSEC E c03 809c06 162c DATA

SINE_VAL 809C C09 The.bstart directive aligns the section name to the next 2 n address boundary following the current section.

Beginning address of the program

DIRECT ADDRESSING page 255 page 254 page  page 3 page 2 page 1 page FFFF 256 Pages 64K page The data address is formed by the concantenation of the eight least significant bits of the data page pointer (DP) with the 16 least significant bits of the instruction word. This results in 256 pages of memory with 64K words per page. The DP must contain the proper value before using direct addressing. DP16 bits of operand

AR0 

AR  AR0 

As shown in the previous slide, the timer (TCLK0) signal is connected to the AIC’s master clock (MCLK) signal. The MCLK signal drives all the key logic signals of the AIC, such as the shift clock, the switched-capacitor filter clocks, and the A/D and D/A timing signals. The timer pulses the TCLK0 signal whenever the timer counter register (0x ) counts up to the timer period register (0x ) value. Then the timer counter register resets to zero and repeats.

AR0 

03C1

AR0  xx INXF0OUTXF0I/OFX0I/OFX1INXF1OUTXF IOF (IO Flag Register)

62H Place the AIC in reset by bringing XFO pin low. This is done by writing an 02 to the CPU’s IOF register.

809c03 809c04 809c05 AR1  809c06 162c Contents of ATABLE = 809c03

The AIC must stay in a reset condition for at least 2 TCLK0 cycles.

AR0 

131

NOTE for this problem that the input A/D is not used. Only the D/A is used to generate the sine wave

AR0 

0E970300

The FSX and FSR frame syncs act as active-low inputs from the AIC. The DX and DR data signals remain active high. Both transmitted and received words are 16 bits in length. This configuration sets the serial port mode for a standard mode (i.e. not continuous mode) with a variable data rate. A variable data rate mode works with AIC’s timing protocol, whereas a fixed data rate mode does not.

AR0  The XMIT (transmit) register is cleared by writing 0s into each bit.

AR0  xx INXF0OUTXF0I/OFX0I/OFX1INXF1OUTXF IOF (IO Flag Register) A logical 0 resets the AIC; a logical 1 brings the AIC out of reset.

The RESET line brought low and remains for 100 NOPs.

809c03 809c04 809c05 AR1  809c06 162c Contents of ATABLE = 809c03 This instruction establishes AR1 as a pointer to the table containing the information that sets the sampling frequency and the bandwidth of the antialiasing and reconstruction filters, as well as other constants used by the DSP.

D15D14D13D12D11D10D9D8D6D5D4D3D7D2D1D0 XXXX TA RA X X c Four values are defined in ATABLE. The first and third values define the sampling rate. TB RB 4892

D15D14D13D12D11D10D9D8D6D5D4D3D7D2D1D0 XXXX T’A R’A The second value in table ATABLE sets TA’ and RA’ to zero implying that the sampling frequency will be determined only by TA and TB.

D15D14D13D12D11D10D9D8D6D5D4D3D7D2D1D0 XXX01 1 XXXXX11001 The fourth value of the table is the contents of the control register. Inserts antialiasing filter Disables loop- back function. Disables auxiliary input. Synchronous transmit receive sections The signal varies between  3 volts.