George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Interrupts and Resets

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Reason for Interrupts You might want certain subroutine executed immediately after internal request and/or request from peripheral devices when certain condition is met. Interrupt provides way to temporarily suspend current program execution in order to execute this subroutine.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Methods of Checking for Requests There are two methods of checking when request to execute certain subroutine is made internally or from peripheral devices. –Polling –Interrupts

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Polling An iterative approach which constantly checks device/register for data Inefficient method for checking when input data has come in because no other instructions can be executed during polling process

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupts Request can be issued at any time CPU suspends execution of main program until instructions in Interrupt Service Routine (ISR) are completely executed Returns to main program after ISR is completed

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Types of Interrupts There are two types of interrupts. –Maskable –Non-Maskable

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table: MON12 not in Use

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405 Maskable Interrupts 27 Maskable Interrupts –Two types of Masking Local –Interrupt enable bit Global –I-bit in CCR –Follows a default priority arrangement Any one interrupt can be promoted to higher priority using HPRIO register 1.IRQ 2.Real-Time Interrupt 3.Standard Timer Channel 0 4.Standard Timer Channel 1 5.Standard Timer Channel 2 6.Standard Timer Channel 3 7.Standard Timer Channel 4 8.Standard Timer Channel 5 9.Standard Timer Channel 6 10.Standard Timer Channel 7 11.Standard Timer Overflow 12.Pulse Accumulator A Overflow 13.Pulse Accumulator Input Edge 14.SPI transfer Complete 15.SCI system 16.ATD 17.Port J 18.CRG PLL Lock 19.CRG Self Clock Mode 20.Flash 21.CAN Wakeup 22.CAN Errors 23.CAN Receive 24.CAN Transmit 25.Port P 26.PWM Emergency Shutdown 27.VREG LVI

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Maskable Interrupts: IRQ Input IRQ pin provides additional external interrupting source IRQE bit in Options Register used to configure IRQ for Edge-Sensitive-Only Operation –IRQE = 0  IRQ is configured for low level sensitive operation –IRQE = 1  IRQ is configured for falling edge-sensitive operation

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Maskable Interrupts: Peripheral Subsystems Interrupts from Internal Peripheral Subsystems –Flag bit, which is set after action takes place –Interrupt enable bit, which enables flag to generate interrupt service

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Priority: Maskable Maskable Interrupts Priority 1.IRQ 2.Real-Time Interrupt 3.Standard Timer Channel 0 4.Standard Timer Channel 1 5.Standard Timer Channel 2 6.Standard Timer Channel 3 7.Standard Timer Channel 4 8.Standard Timer Channel 5 9.Standard Timer Channel 6 10.Standard Timer Channel 7 11.Standard Timer Overflow 12.Pulse Accumulator A Overflow 13.Pulse Accumulator Input Edge 14.SPI transfer Complete 15.SCI system 16.ATD 17.Port J 18.CRG PLL Lock 19.CRG Self Clock Mode 20.Flash 21.CAN Wakeup 22.CAN Errors 23.CAN Receive 24.CAN Transmit 25.Port P 26.PWM Emergency Shutdown 27.VREG LVI Any can be assigned the highest maskable interrupt priority...

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 HPRIO Register for Maskable Interrupts Used to elevate priority of any one maskable interrupt Default is IRQ Set by changing contents of HPRIO (Highest Priority Interrupt Register) Can only be written when I-bit is set

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 HPRIO Register for Maskable Interrupts Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 PSEL7PSEL6PSEL5PSEL4PSEL3PSEL2PSEL1 Address: $001F PSEL[7:1] – Priority Select Bits Selects one interrupts source to be elevated Can only be written while I-bit in the CCR is set Write the low byte of the maskable interrupt vector to HPRIO to elevate that maskable interrupt to the highest priority Ex: writing $DE to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit PSEL7PSEL6PSEL5PSEL4PSEL3PSEL2PSEL1-

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Non-Maskable Interrupts 6 Non-Maskable Interrupts –Follows a default priority arrangement –Interrupts are not subject to global masking Except XIRQ –Global mask is X in CCR 1.POR of RESET pin 2.Clock monitor reset 3.COP watchdog reset 4.Unimplemented instruction trap 5.Software interrupt (SWI) 6.XIRQ interrupt

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Non-Maskable Interrupts: Unimplemented instruction trap Generates interrupt request to Unimplemented instruction trap vector Reinitializes stack pointer once interrupt service is completed Left un-initialized, illegal opcode vector can cause infinite loop causing stack underflow

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Non-Maskable Interrupts: Software Interrupt- SWI Software instruction, thus cannot be interrupted until completed Uninhibited by global mask bits in the CCR Similar to other interrupts, sets I-bit upon servicing

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Non-Maskable Interrupts: XIRQ Enabled by TAP instruction by clearing X-bit upon system initialization After it is cleared, software cannot set X-bit, thus XIRQ is non-maskable Higher priority than any source maskable by I-bit Both X and I bits are automatically set by Reset or recognition of XIRQ interrupt RTI restores X and I bit to pre-interrupt states

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Stacking Order when an Interrupt Occurs Memory Location CPU Registers SPPCL SP-1PCH SP-2IYL SP-3IYH SP-4IXL SP-5IXH SP-6ACCA SP-7ACCB SP-8CCR Last value to be pulled from stack

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vectors Each type of interrupt has associated vector addresses Vector addresses change depending on whether MON12 is in use With MON12 in use, user must use Monitor Interrupt Vector Table

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 MON12 in Use In this case you must write the address of your Interrupt Service Routine to the vector address found in the Monitor Interrupt Vector Table

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table: MON12 in Use … …

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 MON12 in Use Interrupt vector addresses are usually occupied by MON12 With MON12 not in use, starting ISR address must be programmed in standard vector address

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table: MON12 not in Use

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405 Interrupt Flow Interrupt condition is met Restore Registers w/ org. Values Standard Interrupt Table Analyze Priority Store all registers on the Stack Global Masking Local Masking Continue Program Complete Current Instruction A Set (I) or (X) to prohibit another Interrupt Load Address in appropriate vector YES NO YES ISR instruction Clear I or X bit in CCR RTI YES NO B B A Note: Local mask must be cleared prior to performing RTI

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Write a routine to interrupt the MC9S12C32 after 1msec of elapsed time (Assume E = 8 Mhz, Prescaler = 1, MON12 in use). Use TOC3 ORG$1000 LDD#$FFFF/*Delays any TOC3 compares*/ STDTOC3H/*Set output compare to longest time so that you would not have output compare occurring when you are initializing. TOC3H =0056*/ OR SEI/*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT3HI /* BIT5HI = % */ STAATIOS/* Select TOC3 as an output compare*/ STAATFLG1/* Clear TOC3 Interrupt Flag*/ STAATIE/* Enable TOC3 Interrupt */ LDAB#$C0 STAB TCTL2/* PT3 will be high for a successful compare */ LDX#TOC3ISR/* TOC3ISR = $2000, 2 bytes- beginning address of interrupt service routine*/ STXTOC3VEC/* TOC3VEC = $0FE8, This will cause the high byte ($20) of the service routine address to be stored in location $0FE8 and the low byte ($00) to be stored in $0FE9 */ LDDTCNT/* TCNT = $0044 */ ADDD#DLYIOMS/*DLYIOMS = $1F40 = 8000 */ STDTOC3H/* IF not done elsewhere */ CLI/* Clear I bit */ Elapsed Time Example

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Example: Timer Overflow Interrupt TFLG2 EQU $004F *Timer Interrupt Flag 2 TSCR2 EQU $1024 *Timer Interrupt Mask 2 TOFISR EQU $1500 *ISR memory location PROGRAM EQU $1000 STRING EQU $2000 OUTSTRG EQU $FF5E VECTOR EQU $0FDE ORG STRING FCC 'TICK' FCB $04 ORG PROGRAM *Set I-bit to prevent interrupt service during set-up SEI Start timer, turn on TEN LDAA #$80 STAA TSCR2 *TOF Interrupt Enabled STAA TFLG2 *Clears TOF Interrupt Flag LDX #TOVISR *Loads register X with #1500 *Stores content of register X to address Vector incremented STX VECTOR CLR $0001 CLI * Clears I-bit to allow servicing of interrupt LOOP BRA LOOP SWI *Software Interrupt End ORG TOVISR LDAA $0001 * Loads address $0001 content INCA *Increment by 1 STAA $0001 *Stores value back to address CMPA #30 *Compares value to decimal 30 BNE A1 *Loads index register X with content of STRING LDX #STRING JSR OUTSTRG CLR $0001 *Clear address A1 LDAA #$80 *Loads binary STAA TFLG2 *Clears local flag RTI Pre-interrupt service set-up

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Resets Forces the MCU to: assume set of initial conditions begin executing instructions at predetermined starting address.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Resets Like interrupts, resets share concept of vector fetching to force new starting point for further CPU operations. In contrast to interrupts, resets stop completely execution of set of instructions. Also they always rest MCU hardware.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Sources of Resets Power on Reset (POR) External Reset (RESET) Computer Operating Properly (COP) Reset Clock Monitor Reset

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Power-On Resets Power-On Reset (POR) Used only for power-up conditions to initialize MCU internal circuits. Applying Vdd to MCU triggers POR circuit, initiates reset sequence, and starts internal timing circuit clock cycle delay after oscillator becomes active, allows clock generator to stabilize.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 External Reset System reset can also be forced by applying low level to RESET pin. External source must hold pin low for more than 4 cycles. If this happens, pin is further sampled 2 cycles after Low level at sampling instant indicates that reset has been caused by external device.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Computer Operating Properly Reset Protects against software failures When enabled, software to keep free- running watchdog timer from timing out is activated System reset is initiated when software stops executing in the intended sequence

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 COP Reset continued COP is enabled or disabled by setting NOCOP bit in CONFIG register. To change status of COP system, contents of CONFIG register are changed and system reset is initiated. COP timer rate is controlled in OPTION Register. The system E-clock is divided by 2^15 and further scaled by 1, 2 and 4.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Clock Monitor Reset Clock Monitor Reset circuit is based on internal resistor capacitor time delay. If no MCU clock edges are detected within this RC time delay, clock monitor, if set by CME control bit, would generate system reset.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 How the MPU Distinguishes between Internal and External Resets MPU senses whether reset pin rises to logic 1 within two E-clock cycles after internal device releases reset. When reset condition is sensed, RESET pin is driven low by internal device for 4 E-clock cycles, then released. Two E-clock cycles later, it is sampled. If pin is still held low, CPU assumes that external reset has occurred. If pin is high, it indicates that reset was internally initiated.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Occurrence of Reset Affects CPU Memory Map Timer Real-time Interrupt Pulse Accumulator SPI ADC System COP SCI

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Process Flow out of Resets When Reset is triggered Vector fetch (Program counter loaded with contents of specified address) S, X and I bits set in CCR MCU hardware reset Checks for interrupts

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Standby Modes Suspends CPU operation until reset or interrupt occurs Used to reduce power consumption Two standby modes: WAIT STOP

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Standby Modes: WAIT Opcode (WAI) Suspends CPU processing CPU registers are stacked On-chip crystal oscillator remains active Exit WAIT mode through external IRQ, XIRQ, or any internally generated interrupts

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Standby Modes: STOP If S-bit in the CCR is 0, CPU goes into stop mode Else, opcode is treated as NOP All clocks stopped  internal peripherals stopped Retains data in Internal RAM if V DD is maintained CPU state and I/O pin levels are static Exit STOP mode through external interrupts, pending edge-triggered IRQ or RESET pin

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Standby Modes: STOP Recovering through XIRQ X-bit is clear  Returns to stacking sequence leading to normal XIRQ request X-bit is set  Returns to instruction immediately following STOP instruction

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Questions???