Modern Digital System Design Using VHDL: A Practical Introduction Subprograms & Packages Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd.

Slides:

Advertisements

Similar presentations

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

Advertisements

VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

Comprehensive VHDL Module 6 Types November Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.

VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.

COE 561 Digital System Design & Synthesis Introduction to VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum.

COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H.

ELEN 468 Lecture 191 ELEN 468 Advanced Logic Design Lecture 19 VHDL.

Topics of Lecture Structural Model Procedures Functions Overloading.

Programming in VHDL Using Processes. How Processes Run A process is either in suspend mode or is running. For a process to run, there has to be a change.

The IEEE Libraries And Examples Using Functions. Libraries Using the Library Command VHDL allows libraries defined using: library LibraryName; Here, we.

第6章 VHDL NUMBERS, STRINGS, AND EXPRESSIONS 義守大學電機工程學系陳慶瀚

COE 405 Design Organization and Parameterization Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr.

(1) Basic Input and Output © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.

Concordia University 1 Lecture #8 In this lecture we will cover the following material: The standard package, The std_logic_1164  Objects & data Types.

Design Organization and Parameterization Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.

1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

A VHDL Tutorial ENG2410. ENG241/VHDL Tutorial2 Goals Introduce the students to the following: –VHDL as Hardware description language. –How to describe.

IAY 0600 Digital Systems Design

ECE 368 CAD-Based Logic Design Shantanu Dutt Lecture 11 File I/O and Textio in VHDL (courtesy of Karam Chatha, ASU)

7/10/2007DSD,USIT,GGSIPU1 Basic concept of Sequential Design.

VHDL Files & Text IO ECE4623/5623 Computer Hardware Design.

RTL Hardware Design by P. Chu Chapter Basic VHDL program 2. Lexical elements and program format 3. Objects 4. Data type and operators RTL Hardware.

Fall 2004EE 3563 Digital Systems Design EE 3563 VHDL – Basic Language Elements  Identifiers: –basic identifier: composed of a sequence of one or more.

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Digital Logic Design.

Copyright(c) 1996 W. B. Ligon III1 Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component.

VHDL Very High Speed Integrated Circuit Hardware Description Language Shiraz University of shiraz spring 2011.

Electrical and Computer Engineering University of Cyprus LAB 1: VHDL.

(1) Basic Language Concepts © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.

VHDL Basics. VHDL BASICS 2 OUTLINE –Component model –Code model –Entity –Architecture –Identifiers and objects –Operations for relations VHDL ET062G &

L13 – VHDL Language Elements. VHDL Language Elements  Elements needed for FPGA design Types  Basic Types  Resolved Types – special attributes of resolved.

Lecture #7 Page 1 Lecture #7 Agenda 1.VHDL Data Types Announcements 1.n/a ECE 4110– Digital Logic Design.

Chapter 5 Introduction to VHDL. 2 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.

L19 – Resolved Signals. Resolved Signals  What are resolved signals In systems In VHDL Resolution – Isn’t that for resolving conflicts?  Ref: text Unit.

IAY 0600 Digital Systems Design

Concordia University 1 Lecture #8 In this lecture we will cover the following material: The standard package, The std_logic_1164  Objects & data Types.

16/11/2006DSD,USIT,GGSIPU1 Packages The primary purpose of a package is to encapsulate elements that can be shared (globally) among two or more design.

8-Jan-16EE5141 Chapter 6 Subprograms & Packages Subprogram declaration Subprogram body Package declaration Package body Resolution function Subprogram.

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

BASIC VHDL LANGUAGE ELEMENTS Digital Design for Instrumentation with VHDL 1.

VHDL Discussion Subprograms IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1.

Subprograms Lecture 6. Subprograms A subprogram defines a sequential algorithm that performs some computations. Subprograms can be: –1. functions –2.

VHDL Programming Fundamentals Presented By Dr. Pradyut Kumar Biswal Department of Electronics, IIIT Bhubaneswar.

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design.

IAY 0600 Digital Systems Design VHDL discussion Verification: Testbenches Alexander Sudnitson Tallinn University of Technology.

Case Study: Xilinx Synthesis Tool (XST). Arrays & Records 2.

EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09.

Chapter 8. Additional Topics in VHDL 권동혁.

IAY 0600 Digital Systems Design

Introduction To VHDL 홍 원 의.

Basic Language Concepts

Subject Name: FUNDAMENTALS OF HDL Subject Code: 10EC45

Design Entry: Schematic Capture and VHDL

CPE 528: Session #7 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

ECE 434 Advanced Digital System L17

CHAPTER 10 Introduction to VHDL

ECE 434 Advanced Digital System L9

CPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

CPE/EE 422/522 Advanced Logic Design L11

ECE 434 Advanced Digital System L10

VHDL Discussion Subprograms

IAS 0600 Digital Systems Design

CPE 528: Lecture #3 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

VHDL Discussion Subprograms

IAS 0600 Digital Systems Design

VHDL Data Types Module F3.1.

EEL4712 Digital Design (VHDL Tutorial).

Presentation transcript:

Modern Digital System Design Using VHDL: A Practical Introduction Subprograms & Packages Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals

4-2 OutlineOutline n Subprograms Functions Procedures n Examples of functions n Example of procedures n Packages Package declaration section Package body n Design libraries VHDL standard packages IEEE Std_Logic 1164 package n Subprograms Functions Procedures n Examples of functions n Example of procedures n Packages Package declaration section Package body n Design libraries VHDL standard packages IEEE Std_Logic 1164 package

4-3 Subprograms…Subprograms… n Subprograms consist of functions and procedures. n Subprograms are used to Simplify coding, Achieve modularity, Improve readability. n Functions return values and cannot alter values of their parameters. n Procedures used as a statement and can alter values of their parameters. n All statements inside a subprogram are sequential. n Subprograms consist of functions and procedures. n Subprograms are used to Simplify coding, Achieve modularity, Improve readability. n Functions return values and cannot alter values of their parameters. n Procedures used as a statement and can alter values of their parameters. n All statements inside a subprogram are sequential.

4-4 …Subprograms…Subprograms n Subprograms Concurrent Sequential n Concurrent subprograms exist outside of a process or another subprogram. n Sequential subprograms exist in a process statement or another subprogram. n A procedure exists as a separate statement in architecture or process. n A function usually used in assignment statement or expression. n Subprograms Concurrent Sequential n Concurrent subprograms exist outside of a process or another subprogram. n Sequential subprograms exist in a process statement or another subprogram. n A procedure exists as a separate statement in architecture or process. n A function usually used in assignment statement or expression.

4-5 FunctionsFunctions n Function specification: Name of the function Formal parameters of the function Name of the parameter Type of the parameter Mode IN is default & only allowed mode Class constant is default Return type of the function Local declarations n A function body Must contain at least one return statement May not contain a wait statement n Function specification: Name of the function Formal parameters of the function Name of the parameter Type of the parameter Mode IN is default & only allowed mode Class constant is default Return type of the function Local declarations n A function body Must contain at least one return statement May not contain a wait statement

4-6 A Left-Shift Function Subtype Byte IS Bit_Vector (7 Downto 0) Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte IS Variable Result: Byte := V; Begin For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL; Subtype Byte IS Bit_Vector (7 Downto 0) Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte IS Variable Result: Byte := V; Begin For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL;

4-7 Using the Function Architecture Functional Of LeftShifter IS Subtype Byte IS Bit_Vector (7 Downto 0) Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is Variable Result: Byte := V; Begin For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL; Begin Sout <= SLL(Sin, 1, ‘0’) After 12 ns; End Functional; Architecture Functional Of LeftShifter IS Subtype Byte IS Bit_Vector (7 Downto 0) Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is Variable Result: Byte := V; Begin For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL; Begin Sout <= SLL(Sin, 1, ‘0’) After 12 ns; End Functional;

4-8 A Single-Bit Comparator Entity Bit_Comparator IS Port ( a, b,-- data inputs gt,-- previous greater than eq,-- previous equal lt: IN BIT;-- previous less than a_gt_b,-- greater a_eq_b,-- equal a_lt_b: OUT BIT);-- less than End Bit_Comparator; a_gt_b = a. gt + b`. gt + a. b` a_eq_b = a. b. eq + a`. b`. eq a_lt_b = b. lt + a`. lt + b. a` Entity Bit_Comparator IS Port ( a, b,-- data inputs gt,-- previous greater than eq,-- previous equal lt: IN BIT;-- previous less than a_gt_b,-- greater a_eq_b,-- equal a_lt_b: OUT BIT);-- less than End Bit_Comparator; a_gt_b = a. gt + b`. gt + a. b` a_eq_b = a. b. eq + a`. b`. eq a_lt_b = b. lt + a`. lt + b. a`

4-9 A Single-Bit Comparator using Functions Architecture Functional of Bit_Comparator IS Function fgl (w, x, gl: BIT) Return BIT IS Begin Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); End fgl; Function feq (w, x, eq: BIT) Return BIT IS Begin Return (w AND x AND eq) OR (NOT w AND NOT x AND eq); End feq; Begin a_gt_b <= fgl (a, b, gt) after 12 ns; a_eq_b <= feq (a, b, eq) after 12 ns; a_lt_b <= fgl (b, a, lt) after 12 ns; End Functional; Architecture Functional of Bit_Comparator IS Function fgl (w, x, gl: BIT) Return BIT IS Begin Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); End fgl; Function feq (w, x, eq: BIT) Return BIT IS Begin Return (w AND x AND eq) OR (NOT w AND NOT x AND eq); End feq; Begin a_gt_b <= fgl (a, b, gt) after 12 ns; a_eq_b <= feq (a, b, eq) after 12 ns; a_lt_b <= fgl (b, a, lt) after 12 ns; End Functional;

4-10 Binary to Integer Conversion Function Function To_Integer (Bin : BIT_VECTOR) Return Integer IS Variable Result: Integer; Begin Result := 0; For I IN Bin`RANGE Loop If Bin(I) = ‘1’ then Result := Result + 2**I; End if; End Loop; Return Result; End To_Integer; Function To_Integer (Bin : BIT_VECTOR) Return Integer IS Variable Result: Integer; Begin Result := 0; For I IN Bin`RANGE Loop If Bin(I) = ‘1’ then Result := Result + 2**I; End if; End Loop; Return Result; End To_Integer;

4-11 Execution of a Function n Actual parameters are evaluated. n Actuals are associated with their formals. n Sequential statements are executed in order. n Function exits when a return statement is executed. n Return must supply a value of the return type. n Direct and indirect recursion is allowed. n Argument modification is not allowed. n Execution of a wait statement is not allowed. n Actual parameters are evaluated. n Actuals are associated with their formals. n Sequential statements are executed in order. n Function exits when a return statement is executed. n Return must supply a value of the return type. n Direct and indirect recursion is allowed. n Argument modification is not allowed. n Execution of a wait statement is not allowed.

4-12 Procedure Specification n Name of the procedure n Formal parameters of the procedure Class of the parameter optional defaults to constant Name of the parameter Mode of the parameter optional Defaults to IN Type of the parameter n Local declarations n Name of the procedure n Formal parameters of the procedure Class of the parameter optional defaults to constant Name of the parameter Mode of the parameter optional Defaults to IN Type of the parameter n Local declarations

4-13 A Left-Shift Procedure Procedure SLL ( Signal Vin: In Byte; Signal Vout: Out Byte; N: Natural; Fill: Bit; ShiftTime: Time) IS Variable Temp: Byte := Vin; Begin For I IN 1 To N Loop Temp := Temp (6 Downto 0) & Fill; End Loop ; Vout <= Temp After N * ShiftTime; End SLL; Procedure SLL ( Signal Vin: In Byte; Signal Vout: Out Byte; N: Natural; Fill: Bit; ShiftTime: Time) IS Variable Temp: Byte := Vin; Begin For I IN 1 To N Loop Temp := Temp (6 Downto 0) & Fill; End Loop ; Vout <= Temp After N * ShiftTime; End SLL;

4-14 Using the Procedure Architecture Procedural of LeftShifter is Subtype Byte is Bit_Vector (7 downto 0) Procedure SLL (Signal Vin : In; Signal Vout :out Byte; N: Natural; Fill: Bit; ShiftTime: Time) IS Variable Temp: Byte := Vin; Begin For I IN 1 To N Loop Temp := Temp (6 downto 0) & Fill; End Loop; Vout <= Temp after N * ShiftTime; End SLL; Begin Process (Sin) Begin SLL(Sin, Sout, 1, ‘0’, 12 ns) ; End process; End Procedural; Architecture Procedural of LeftShifter is Subtype Byte is Bit_Vector (7 downto 0) Procedure SLL (Signal Vin : In; Signal Vout :out Byte; N: Natural; Fill: Bit; ShiftTime: Time) IS Variable Temp: Byte := Vin; Begin For I IN 1 To N Loop Temp := Temp (6 downto 0) & Fill; End Loop; Vout <= Temp after N * ShiftTime; End SLL; Begin Process (Sin) Begin SLL(Sin, Sout, 1, ‘0’, 12 ns) ; End process; End Procedural;

4-15 Binary to Integer Conversion Procedure Procedure Bin2Int (Bin : IN BIT_VECTOR; Int: OUT Integer) IS Variable Result: Integer; Begin Result := 0; For I IN Bin`RANGE Loop If Bin(I) = ‘1’ Then Result := Result + 2**I; End If; End Loop; Int := Result; End Bin2Int; Procedure Bin2Int (Bin : IN BIT_VECTOR; Int: OUT Integer) IS Variable Result: Integer; Begin Result := 0; For I IN Bin`RANGE Loop If Bin(I) = ‘1’ Then Result := Result + 2**I; End If; End Loop; Int := Result; End Bin2Int;

4-16 Integer to Binary Conversion Procedure Procedure Int2Bin (Int: IN Integer; Bin : OUT BIT_VECTOR) IS Variable Tmp: Integer; Begin Tmp := Int; For I IN 0 To (Bin`Length - 1) Loop If ( Tmp MOD 2 = 1) Then Bin(I) := ‘1’; Else Bin(I) := ‘0’; End If; Tmp := Tmp / 2; End Loop; End Int2Bin; Procedure Int2Bin (Int: IN Integer; Bin : OUT BIT_VECTOR) IS Variable Tmp: Integer; Begin Tmp := Int; For I IN 0 To (Bin`Length - 1) Loop If ( Tmp MOD 2 = 1) Then Bin(I) := ‘1’; Else Bin(I) := ‘0’; End If; Tmp := Tmp / 2; End Loop; End Int2Bin;

4-17 Using Procedures in a Test Bench … Architecture Procedural of Nibble_Comparator_Test IS Component Comp4 Port (a, b: IN Bit_Vector(3 Downto 0); gt, eq, lt: IN Bit; a_gt_b, a_eq_b, a_lt_b: OUT BIT); End Component; Signal a, b: Bit_Vector (3 downto 0); Signal eql, gtr, lse: BIT; Signal Vdd: BIT := ‘1’; Signal GND: BIT := ‘0’; Begin a1: Comp4 Port Map (a, b, GND, Vdd, GND, gtr, eql, lss); Apply_Data (a, 00&15&14&12&10&01, 500 ns); Apply_Data (b, 00&14&15&06&10&02, 500 ns); End Procedural; Architecture Procedural of Nibble_Comparator_Test IS Component Comp4 Port (a, b: IN Bit_Vector(3 Downto 0); gt, eq, lt: IN Bit; a_gt_b, a_eq_b, a_lt_b: OUT BIT); End Component; Signal a, b: Bit_Vector (3 downto 0); Signal eql, gtr, lse: BIT; Signal Vdd: BIT := ‘1’; Signal GND: BIT := ‘0’; Begin a1: Comp4 Port Map (a, b, GND, Vdd, GND, gtr, eql, lss); Apply_Data (a, 00&15&14&12&10&01, 500 ns); Apply_Data (b, 00&14&15&06&10&02, 500 ns); End Procedural;

4-18 …Using Procedures in a Test Bench Type Integers IS Array (0 to 5) of Integer; Procedure Apply_Data ( Signal Target: OUT Bit_Vector (3 Downto 0); Constant Values: IN Integers; Constant Period: IN Time) IS Variable Buf: Bit_Vector (3 Downto 0); Begin For I IN 0 To 5 Loop Int2Bin (Values(I), Buf); Target <= Transport Buf After I * Period; End Loop; End Apply_Data; Type Integers IS Array (0 to 5) of Integer; Procedure Apply_Data ( Signal Target: OUT Bit_Vector (3 Downto 0); Constant Values: IN Integers; Constant Period: IN Time) IS Variable Buf: Bit_Vector (3 Downto 0); Begin For I IN 0 To 5 Loop Int2Bin (Values(I), Buf); Target <= Transport Buf After I * Period; End Loop; End Apply_Data;

4-19 Executing a Procedure n Actual parameters are evaluated. n Actuals are associated with their formals. n Sequential statements are executed in order. n Procedure exits when End of the procedure is reached A return statement is executed; no value allowed n Direct and indirect recursion is allowed. n Argument modification is allowed. n Execution of a wait statement is allowed. n Actual parameters are evaluated. n Actuals are associated with their formals. n Sequential statements are executed in order. n Procedure exits when End of the procedure is reached A return statement is executed; no value allowed n Direct and indirect recursion is allowed. n Argument modification is allowed. n Execution of a wait statement is allowed.

4-20 Packages…Packages… n A package is a common storage area used to hold data to be shared among a number of entities. n Packages can encapsulate subprograms to be shared. n A package consists of Declaration section Body section n The package declaration section contains subprogram declarations, not bodies. n The package body contains the subprograms’ bodies. n The package declaration defines the interface for the package. n A package is a common storage area used to hold data to be shared among a number of entities. n Packages can encapsulate subprograms to be shared. n A package consists of Declaration section Body section n The package declaration section contains subprogram declarations, not bodies. n The package body contains the subprograms’ bodies. n The package declaration defines the interface for the package.

4-21 …Packages…Packages n All items declared in the package declaration section are visible to any design unit that uses the package. n A package is used by the USE clause. n The interface to a package consists of any subprograms or deferred constants declared in the package declaration. n The subprogram and deferred constant declarations must have a corresponding subprogram body and deferred constant value in the package body. n Package body May contain other declarations needed solely within the package body. Not visible to external design units. n All items declared in the package declaration section are visible to any design unit that uses the package. n A package is used by the USE clause. n The interface to a package consists of any subprograms or deferred constants declared in the package declaration. n The subprogram and deferred constant declarations must have a corresponding subprogram body and deferred constant value in the package body. n Package body May contain other declarations needed solely within the package body. Not visible to external design units.

4-22 Package Declaration n The package declaration section can contain: Subprogram declaration Type, subtype declaration Constant, deferred constant declaration Signal declaration creates a global signal File declaration Alias declaration Component declaration Attribute declaration, a user-defined attribute Attribute specification Use clause n The package declaration section can contain: Subprogram declaration Type, subtype declaration Constant, deferred constant declaration Signal declaration creates a global signal File declaration Alias declaration Component declaration Attribute declaration, a user-defined attribute Attribute specification Use clause

4-23 Package Body n The package body main purpose is Define the values of deferred constants Specify the subprogram bodies for subprograms declared in the package declaration n The package body can also contain: Subprogram declaration Subprogram body Type, subtype declaration Constant declaration, which fills in the value for deferred constants File declaration Alias declaration Use clause n The package body main purpose is Define the values of deferred constants Specify the subprogram bodies for subprograms declared in the package declaration n The package body can also contain: Subprogram declaration Subprogram body Type, subtype declaration Constant declaration, which fills in the value for deferred constants File declaration Alias declaration Use clause

4-24 Package Example… Package Shifters IS Subtype Byte IS Bit_Vector (7 Downto 0); Function SLL (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte; Function SRL (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte; Function SLA (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte; Function SRA (V: Byte; N: Natural) Return Byte; Function RLL (V: Byte; N: Natural) Return Byte; Function RRL (V: Byte; N: Natural) Return Byte; End Shifters; Package Shifters IS Subtype Byte IS Bit_Vector (7 Downto 0); Function SLL (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte; Function SRL (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte; Function SLA (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte; Function SRA (V: Byte; N: Natural) Return Byte; Function RLL (V: Byte; N: Natural) Return Byte; Function RRL (V: Byte; N: Natural) Return Byte; End Shifters;

4-25 …Package Example… Package Body Shifters IS Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is Variable Result: Byte := V; Begin If N >= 8 Then Return (Others => Fill); End If; For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL;. End Shifters; Package Body Shifters IS Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is Variable Result: Byte := V; Begin If N >= 8 Then Return (Others => Fill); End If; For I IN 1 To N Loop Result := Result (6 Downto 0) & Fill; End Loop; Return Result; End SLL;. End Shifters;

4-26 …Package Example USE WORK.Shifters.ALL Architecture Functional of LeftShifter IS Begin Sout <= SLL(Sin, 1, ‘0’) After 12 ns; End Functional; USE WORK.Shifters.ALL Architecture Functional of LeftShifter IS Begin Sout <= SLL(Sin, 1, ‘0’) After 12 ns; End Functional;

4-27 Another Package Example… Package Basic_Utilities IS Type Integers IS Array (0 to 5) of Integer; Function fgl (w, x, gl: BIT) Return BIT; Function feq (w, x, eq: BIT) Return BIT; Procedure Bin2Int (Bin : IN BIT_VECTOR; Int: OUT Integer); Procedure Int2Bin (Int: IN Integer; Bin : OUT BIT_VECTOR); Procedure Apply_Data ( Signal Target: OUT Bit_Vector (3 Downto 0); Constant Values: IN Integers; Constant Period: IN Time); Function To_Integer (Bin : BIT_VECTOR) Return Integer; End Basic_Utilities; Package Basic_Utilities IS Type Integers IS Array (0 to 5) of Integer; Function fgl (w, x, gl: BIT) Return BIT; Function feq (w, x, eq: BIT) Return BIT; Procedure Bin2Int (Bin : IN BIT_VECTOR; Int: OUT Integer); Procedure Int2Bin (Int: IN Integer; Bin : OUT BIT_VECTOR); Procedure Apply_Data ( Signal Target: OUT Bit_Vector (3 Downto 0); Constant Values: IN Integers; Constant Period: IN Time); Function To_Integer (Bin : BIT_VECTOR) Return Integer; End Basic_Utilities;

4-28 …Another Package Example… Package Body Basic_Utilities IS Function fgl (w, x, gl: BIT) Return BIT IS Begin Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); End fgl; Function feq (w, x, eq: BIT) Return BIT IS Begin Return (w AND x AND eq) OR (NOT w AND NOT x AND eq); End feq;. End Basic_Utilities; Package Body Basic_Utilities IS Function fgl (w, x, gl: BIT) Return BIT IS Begin Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); End fgl; Function feq (w, x, eq: BIT) Return BIT IS Begin Return (w AND x AND eq) OR (NOT w AND NOT x AND eq); End feq;. End Basic_Utilities;

4-29 …Another Package Example USE WORK.Basic_Utilities.ALL Architecture Functional of Bit_Comparator IS Begin a_gt_b <= fgl (a, b, gt) after 12 ns; a_eq_b <= feq (a, b, eq) after 12 ns; a_lt_b <= fgl (b, a, lt) after 12 ns; End Functional; USE WORK.Basic_Utilities.ALL Architecture Functional of Bit_Comparator IS Begin a_gt_b <= fgl (a, b, gt) after 12 ns; a_eq_b <= feq (a, b, eq) after 12 ns; a_lt_b <= fgl (b, a, lt) after 12 ns; End Functional;

4-30 Design Libraries… n VHDL supports the use of design libraries for categorizing components or utilities. n Applications of libraries include Sharing of components between designers Grouping components of standard logic families Categorizing special-purpose utilities such as subprograms or types n Exiting libraries STD Library Contains the STANDARD and TEXTIO packages Contains all the standard types & utilities Visible to all designs WORK library Root library for the user n VHDL supports the use of design libraries for categorizing components or utilities. n Applications of libraries include Sharing of components between designers Grouping components of standard logic families Categorizing special-purpose utilities such as subprograms or types n Exiting libraries STD Library Contains the STANDARD and TEXTIO packages Contains all the standard types & utilities Visible to all designs WORK library Root library for the user

4-31 …Design Libraries n IEEE library Contains VHDL-related standards Contains the std_logic_1164 (IEEE ) package Defines a nine values logic system n To make a library visible to a design LIBRARY libname; n The following statement is assumed by all designs LIBRARY WORK; n To use the std_logic_1164 packge LIBRARY IEEE USE IEEE.std_logic_1164.ALL n IEEE library Contains VHDL-related standards Contains the std_logic_1164 (IEEE ) package Defines a nine values logic system n To make a library visible to a design LIBRARY libname; n The following statement is assumed by all designs LIBRARY WORK; n To use the std_logic_1164 packge LIBRARY IEEE USE IEEE.std_logic_1164.ALL

4-32 Standard Package… n Defines primitive types, subtypes, and functions. n The package STANDARD is usually integrated directly in the simulation or synthesis program. n It contains all basic types: Boolean, bit, bit_vector, character, integer, and the like. n Additional logical, comparison and arithmetic operators are defined for these types within the package. n The package STANDARD does not have to be explicitly included by the use statement. n Defines primitive types, subtypes, and functions. n The package STANDARD is usually integrated directly in the simulation or synthesis program. n It contains all basic types: Boolean, bit, bit_vector, character, integer, and the like. n Additional logical, comparison and arithmetic operators are defined for these types within the package. n The package STANDARD does not have to be explicitly included by the use statement.

4-33 …Standard Package… Package Standard IS Type Boolean IS (false, true); Type Bit is (‘0’, ‘1’); Type Character IS ( nul, soh, stx, ……); Type Sensitivity_level IS (Note, Warning, Error, Failure); Type Integer IS Range – to ; Type Real IS Range –1.0E308 to 1.0E308; Subtype Natural IS Integer Range 0 to Integer`High; Subtype Positive IS Integer Range 1 to Integer`High; Type String IS Array (positive Range <>) of Character; Package Standard IS Type Boolean IS (false, true); Type Bit is (‘0’, ‘1’); Type Character IS ( nul, soh, stx, ……); Type Sensitivity_level IS (Note, Warning, Error, Failure); Type Integer IS Range – to ; Type Real IS Range –1.0E308 to 1.0E308; Subtype Natural IS Integer Range 0 to Integer`High; Subtype Positive IS Integer Range 1 to Integer`High; Type String IS Array (positive Range <>) of Character;

4-34 …Standard Package Type Bit_Vector IS Array (Natural Range <>) of Bit; Type Time IS Range – to Units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns;ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; End Units; Subtype Delay_length IS Time Range 0 fs to Time`High; Impure Function Now Return Delay_Length;. End Standard; Type Bit_Vector IS Array (Natural Range <>) of Bit; Type Time IS Range – to Units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns;ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; End Units; Subtype Delay_length IS Time Range 0 fs to Time`High; Impure Function Now Return Delay_Length;. End Standard;

4-35 TEXTIO Package… n Defines types, procedures, and functions for standard text I/O from ASCII files. n This package is also a part of the library STD. n It is not included in every VHDL description by default. n Therefore, if required, it has to be included by the statement USE STD.TEXTIO.all;. n Defines types, procedures, and functions for standard text I/O from ASCII files. n This package is also a part of the library STD. n It is not included in every VHDL description by default. n Therefore, if required, it has to be included by the statement USE STD.TEXTIO.all;.

4-36 …TEXTIO Package Package TEXTIO IS Type Line IS Access String; Type Text IS File of String; Type Side IS (Right, Left); Subtype Width IS Natural; File Input: Text Open Read_Mode IS “STD_INPUT”; File Output: Text Open Write_Mode IS “STD_OUTPUT”; Procedure Readline (File F: Text; L: Out Line); Procedure Writeline (File F: Text; L: Inout Line); Function Endfile (File F: Text) Return Boolean; End TEXTIO; Package TEXTIO IS Type Line IS Access String; Type Text IS File of String; Type Side IS (Right, Left); Subtype Width IS Natural; File Input: Text Open Read_Mode IS “STD_INPUT”; File Output: Text Open Write_Mode IS “STD_OUTPUT”; Procedure Readline (File F: Text; L: Out Line); Procedure Writeline (File F: Text; L: Inout Line); Function Endfile (File F: Text) Return Boolean; End TEXTIO;

4-37 Example using TEXTIO Package… USE STD.TEXTIO.ALL Entity Square IS Port (Go : IN Std_Logic); END Squae; Architecture Simple of Squae IS Begin Process (Go) File Infile : Text IS IN “example1”; File Outfile : Text IS OUT “Outfile1”; Variable Out_Line, My_Line : Line; Variable Int_Val : Integer; Begin While Not ( Endfile(Infile) ) Loop Readline( Infile, My_Line); -- read a line from the input file USE STD.TEXTIO.ALL Entity Square IS Port (Go : IN Std_Logic); END Squae; Architecture Simple of Squae IS Begin Process (Go) File Infile : Text IS IN “example1”; File Outfile : Text IS OUT “Outfile1”; Variable Out_Line, My_Line : Line; Variable Int_Val : Integer; Begin While Not ( Endfile(Infile) ) Loop Readline( Infile, My_Line); -- read a line from the input file

4-38 …Example using TEXTIO Package Read( My_Line, Int_Val); -- read a value from the line Int_Value := Int_Val ** 2; -- squae the value Write( Out_Line, Int_Val); -- write the squared value to the line WriteLine( Outfile, Out_Line); -- write the line to the output file End Loop; End Process; End Simple; Read( My_Line, Int_Val); -- read a value from the line Int_Value := Int_Val ** 2; -- squae the value Write( Out_Line, Int_Val); -- write the squared value to the line WriteLine( Outfile, Out_Line); -- write the line to the output file End Loop; End Process; End Simple;

4-39 Package IEEE.Std_Logic_1164 … Package Std_Logic_1164 IS -- logic state system (unresolved) Type Std_Ulogic IS ( ‘U’, -- Uninitialized ‘X’, -- Forcing Unknown ‘0’,-- Forcing 0 ‘1’,-- Forcing 1 ‘Z’,-- High Impedance ‘W’,-- Weak Unknown ‘L’,-- Weak 0 ‘H’,-- Weak 1 ‘-’);-- Don’t Care -- unconstrained array of std_ulogic Type Std_Ulogic_Vector IS Array ( Natural Range <>) of Std_Ulogic; Package Std_Logic_1164 IS -- logic state system (unresolved) Type Std_Ulogic IS ( ‘U’, -- Uninitialized ‘X’, -- Forcing Unknown ‘0’,-- Forcing 0 ‘1’,-- Forcing 1 ‘Z’,-- High Impedance ‘W’,-- Weak Unknown ‘L’,-- Weak 0 ‘H’,-- Weak 1 ‘-’);-- Don’t Care -- unconstrained array of std_ulogic Type Std_Ulogic_Vector IS Array ( Natural Range <>) of Std_Ulogic;

4-40 …Package IEEE.Std_Logic_1164 … -- Resolution function Function Resolved ( S: Std_Ulogic_Vector) Return Std_Ulogic; -- Industry standard logic type Subtype Std_Logic IS Resolved Std_Ulogic; -- Unconstrained array of Std_Logic Type Std_Logic_Vector IS Array ( Natueal Range <>) of Std_Logic; -- Common subtypes Subtype X01 IS Resolved Std_Ulogic Range ‘X’ To ‘1’; -- (‘X’, ‘0’, ‘1’); Subtype X01Z IS Resolved Std_Ulogic Range ‘X’ To ‘Z’; -- (‘X’, ‘0’, ‘1’, ‘Z’); Subtype UX01 IS Resolved Std_Ulogic Range ‘U’ To ‘1’; -- (‘U’, ‘X’, ‘0’, ‘1’); Subtype UX01Z IS Resolved Std_Ulogic Range ‘U’ To ‘Z’; -- (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’); -- Resolution function Function Resolved ( S: Std_Ulogic_Vector) Return Std_Ulogic; -- Industry standard logic type Subtype Std_Logic IS Resolved Std_Ulogic; -- Unconstrained array of Std_Logic Type Std_Logic_Vector IS Array ( Natueal Range <>) of Std_Logic; -- Common subtypes Subtype X01 IS Resolved Std_Ulogic Range ‘X’ To ‘1’; -- (‘X’, ‘0’, ‘1’); Subtype X01Z IS Resolved Std_Ulogic Range ‘X’ To ‘Z’; -- (‘X’, ‘0’, ‘1’, ‘Z’); Subtype UX01 IS Resolved Std_Ulogic Range ‘U’ To ‘1’; -- (‘U’, ‘X’, ‘0’, ‘1’); Subtype UX01Z IS Resolved Std_Ulogic Range ‘U’ To ‘Z’; -- (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’);

4-41 …Package IEEE.Std_Logic_1164 … -- Overloaded logical operators Function “AND” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “NAND” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “OR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “NOR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “XOR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “XNOR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “NOT” (l: Std_Ulogic ) Return UX01; -- Vectorized overloaded logical operators Function “AND” (l, R: Std_Logic_Vector) Return Std_Logic_Vector; Function “AND” (l, R: Std_Ulogic_Vector) Return Std_Ulogic_Vector;. -- Overloaded logical operators Function “AND” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “NAND” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “OR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “NOR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “XOR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “XNOR” (l: Std_Ulogic; R: Std_Ulogic) Return UX01; Function “NOT” (l: Std_Ulogic ) Return UX01; -- Vectorized overloaded logical operators Function “AND” (l, R: Std_Logic_Vector) Return Std_Logic_Vector; Function “AND” (l, R: Std_Ulogic_Vector) Return Std_Ulogic_Vector;.

4-42 …Package IEEE.Std_Logic_1164 … -- Shift operators Function “SLL” (A: Std_Logic_Vector; N: Integer) Return Std_Logic_Vector; Function “SRL” (A: Std_Logic_Vector; N: Integer) Return Std_Logic_Vector; Function “SLA” (A: Std_Logic_Vector; N: Integer) Return Std_Logic_Vector; Function “SRA” (A: Std_Logic_Vector; N: Integer) ReturnStd_Logic_Vector; Function “ROL” (A: Std_Logic_Vector; N: Integer) ReturnStd_Logic_Vector; Function “ROR” (A: Std_Logic_Vector; N: Integer) ReturnStd_Logic_Vector; -- Conversion functions Function To_Bit (S: Std_Ulogic; Xmap: Bit := ‘0’) Return Bit; Function To_BitVector (S: Std_Logic_Vector; Xmap: Bit := ‘0’) Return Bit_Vector; Function To_StdLogicVector (B: Bit_Vector) Return Std_Logic_Vector; -- Shift operators Function “SLL” (A: Std_Logic_Vector; N: Integer) Return Std_Logic_Vector; Function “SRL” (A: Std_Logic_Vector; N: Integer) Return Std_Logic_Vector; Function “SLA” (A: Std_Logic_Vector; N: Integer) Return Std_Logic_Vector; Function “SRA” (A: Std_Logic_Vector; N: Integer) ReturnStd_Logic_Vector; Function “ROL” (A: Std_Logic_Vector; N: Integer) ReturnStd_Logic_Vector; Function “ROR” (A: Std_Logic_Vector; N: Integer) ReturnStd_Logic_Vector; -- Conversion functions Function To_Bit (S: Std_Ulogic; Xmap: Bit := ‘0’) Return Bit; Function To_BitVector (S: Std_Logic_Vector; Xmap: Bit := ‘0’) Return Bit_Vector; Function To_StdLogicVector (B: Bit_Vector) Return Std_Logic_Vector;

4-43 …Package IEEE.Std_Logic_1164 … -- Strength strippers and type converters Function To_X01 (S: Std_Logic_Vector) Return Std_Logic_Vector; Function To_X01 (S: Bit_Vector) Return Std_Logic_Vector; Function To_X01 (S: Bit ) Return X01; Function To_X01Z (S: Std_Logic_Vector) Return Std_Logic_Vector; Function To_X01Z (S: Bit_Vector) Return Std_Logic_Vector; Function To_X01Z (S: Bit ) Return X01Z; Function To_UX01 (S: Std_Logic_Vector) Return Std_Logic_Vector; Function To_UX01 (S: Bit_Vector) Return Std_Logic_Vector; Function To_UX01 (S: Bit ) Return UX01; -- Strength strippers and type converters Function To_X01 (S: Std_Logic_Vector) Return Std_Logic_Vector; Function To_X01 (S: Bit_Vector) Return Std_Logic_Vector; Function To_X01 (S: Bit ) Return X01; Function To_X01Z (S: Std_Logic_Vector) Return Std_Logic_Vector; Function To_X01Z (S: Bit_Vector) Return Std_Logic_Vector; Function To_X01Z (S: Bit ) Return X01Z; Function To_UX01 (S: Std_Logic_Vector) Return Std_Logic_Vector; Function To_UX01 (S: Bit_Vector) Return Std_Logic_Vector; Function To_UX01 (S: Bit ) Return UX01;

4-44 …Package IEEE.Std_Logic_1164 … -- Edge detection Function Rising_Edge (Signal S: Std_Ulogic) Return Boolean; Function Falling_Edge (Signal S: Std_Ulogic) Return Boolean; -- Object contains unknown Function Is_X (Signal S: Std_Ulogic_Vector) Return Boolean; Function Is_X (Signal S: Std_Logic_Vector) Return Boolean; Function Is_X (Signal S: Std_Ulogic) Return Boolean; End Std_Logic_1164; -- Edge detection Function Rising_Edge (Signal S: Std_Ulogic) Return Boolean; Function Falling_Edge (Signal S: Std_Ulogic) Return Boolean; -- Object contains unknown Function Is_X (Signal S: Std_Ulogic_Vector) Return Boolean; Function Is_X (Signal S: Std_Logic_Vector) Return Boolean; Function Is_X (Signal S: Std_Ulogic) Return Boolean; End Std_Logic_1164;

4-45 Package Body: IEEE.Std_Logic_1164 Package Body Std_Logic_1164 IS Type StdLogic_Table IS ARRAY (Std_Ulogic, Std_Ulogic) of Std_Ulogic; Constant Resolution_Table: StdLogic_Table := ( | U X 0 1 Z W L H - | | ( ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’), -- | U | ( ‘U’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’), -- | X | ( ‘U’, ‘X’, ‘0’, ‘X’, ‘0’, ‘0’, ‘0’, ‘0’, ‘X’), -- | 0 | ( ‘U’, ‘X’, ‘X’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘X’), -- | 1 | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘X’), -- | Z | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘W’, ‘W’, ‘W’, ‘W’, ‘X’), -- | W | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘L’, ‘W’, ‘L’, ‘W’, ‘X’), -- | L | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘H’, ‘W’, ‘W’, ‘H’, ‘X’), -- | H | ( ‘U’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’)) ; -- | - | Package Body Std_Logic_1164 IS Type StdLogic_Table IS ARRAY (Std_Ulogic, Std_Ulogic) of Std_Ulogic; Constant Resolution_Table: StdLogic_Table := ( | U X 0 1 Z W L H - | | ( ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’, ‘U’), -- | U | ( ‘U’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’), -- | X | ( ‘U’, ‘X’, ‘0’, ‘X’, ‘0’, ‘0’, ‘0’, ‘0’, ‘X’), -- | 0 | ( ‘U’, ‘X’, ‘X’, ‘1’, ‘1’, ‘1’, ‘1’, ‘1’, ‘X’), -- | 1 | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘X’), -- | Z | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘W’, ‘W’, ‘W’, ‘W’, ‘X’), -- | W | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘L’, ‘W’, ‘L’, ‘W’, ‘X’), -- | L | ( ‘U’, ‘X’, ‘0’, ‘1’, ‘H’, ‘W’, ‘W’, ‘H’, ‘X’), -- | H | ( ‘U’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’)) ; -- | - |

4-46 The Resolution Function Function Resolved ( S: Std_Ulogic_Vector) Return Std_Ulogic IS Variable Result: Std_Ulogic := ‘Z’; Begin If (S’Length = 1) Then Return S(S’Low); Else For I IN S’Range Loop Result := Resolution_Table(Result, S(I) ); End Loop; End If; Return Result; End Resolved; Function Resolved ( S: Std_Ulogic_Vector) Return Std_Ulogic IS Variable Result: Std_Ulogic := ‘Z’; Begin If (S’Length = 1) Then Return S(S’Low); Else For I IN S’Range Loop Result := Resolution_Table(Result, S(I) ); End Loop; End If; Return Result; End Resolved;

4-47 Some Conversion Functions … Function To_BitVector (S: Std_Logic_Vector; Xmap: Bit := ‘0’) Return Bit_Vector IS Alias SV: Std_Logic_Vector (S’Length-1 Downto 0) IS S; Variable Result: Bit_Vector (S’Length-1 Downto 0); Begin For I IN Result’Range Loop Case SV(I) IS When ‘0’ | ‘L’ => Result(I) := ‘0’; When ‘1’ | ‘H’ => Result(I) := ‘1’; When Others => Result(I) := xmap; End Case; End Loop; Return Result; End; Function To_BitVector (S: Std_Logic_Vector; Xmap: Bit := ‘0’) Return Bit_Vector IS Alias SV: Std_Logic_Vector (S’Length-1 Downto 0) IS S; Variable Result: Bit_Vector (S’Length-1 Downto 0); Begin For I IN Result’Range Loop Case SV(I) IS When ‘0’ | ‘L’ => Result(I) := ‘0’; When ‘1’ | ‘H’ => Result(I) := ‘1’; When Others => Result(I) := xmap; End Case; End Loop; Return Result; End;

4-48 …Some Conversion Functions Type Logic_X01_Table IS Array (Std_Ulogic’Low To Std_Ulogic’High) of X01; Constant Cvt_to_X01 : Logic_X01_Table :=( --‘U’,‘X’,‘0’,‘1’,‘Z’,‘W’,‘L’,‘H’,‘-’ ‘X’,‘X’,‘0’,‘1’,‘X’,‘X’,‘0’,‘1’,‘X’); Function To_X01 (S: Std_Logic_Vector) Return Std_Logic_Vector IS Alias SV: Std_Logic_Vector (1 To S’Length) IS S; Variable Result: Std_Logic_Vector (1 To S’Length) ; Begin For I IN Result’Range Loop Result(I) := Cvt_to_X01 (SV(I) ); End Loop; Return Result; End; Type Logic_X01_Table IS Array (Std_Ulogic’Low To Std_Ulogic’High) of X01; Constant Cvt_to_X01 : Logic_X01_Table :=( --‘U’,‘X’,‘0’,‘1’,‘Z’,‘W’,‘L’,‘H’,‘-’ ‘X’,‘X’,‘0’,‘1’,‘X’,‘X’,‘0’,‘1’,‘X’); Function To_X01 (S: Std_Logic_Vector) Return Std_Logic_Vector IS Alias SV: Std_Logic_Vector (1 To S’Length) IS S; Variable Result: Std_Logic_Vector (1 To S’Length) ; Begin For I IN Result’Range Loop Result(I) := Cvt_to_X01 (SV(I) ); End Loop; Return Result; End;

4-49 Edge Detectors Function Rising_Edge (Signal S: Std_Ulogic) Return Boolean IS Begin Return (S’Event AND (To_X01(S) = ‘1’) AND (To_X01(S’Last_Value) = ‘0’) ); End; Function Falling_Edge (Signal S: Std_Ulogic) Return Boolean IS Begin Return (S’Event AND (To_X01(S) = ‘0’) AND (To_X01(S’Last_Value) = ‘1’) ); End; Function Rising_Edge (Signal S: Std_Ulogic) Return Boolean IS Begin Return (S’Event AND (To_X01(S) = ‘1’) AND (To_X01(S’Last_Value) = ‘0’) ); End; Function Falling_Edge (Signal S: Std_Ulogic) Return Boolean IS Begin Return (S’Event AND (To_X01(S) = ‘0’) AND (To_X01(S’Last_Value) = ‘1’) ); End;

4-50 Unknown Detection Function Is_X (Signal S: Std_Logic_Vector) Return Boolean IS Begin For I IN Result’Range Loop Case S(I) IS When ‘U’ | ‘X’ | ‘Z’ | ‘W’ | ‘-’ => Return True; When Others => NULL; End Case; End Loop; Return False; End; End std_logic_1164; Function Is_X (Signal S: Std_Logic_Vector) Return Boolean IS Begin For I IN Result’Range Loop Case S(I) IS When ‘U’ | ‘X’ | ‘Z’ | ‘W’ | ‘-’ => Return True; When Others => NULL; End Case; End Loop; Return False; End; End std_logic_1164;

4-51 SummarySummary n Subprograms consist of functions and procedures Functions have only input parameters and a single return value. Procedures can have any number of IN, OUT, and INOUT parameters. n Packages are used to encapsulate information that is to be shared among multiple design units. n Packages consist of: Package declaration in which all of the type, subprogram, and other declarations exist. Package body in which subprogram bodies and deferred constants exist. n Subprograms consist of functions and procedures Functions have only input parameters and a single return value. Procedures can have any number of IN, OUT, and INOUT parameters. n Packages are used to encapsulate information that is to be shared among multiple design units. n Packages consist of: Package declaration in which all of the type, subprogram, and other declarations exist. Package body in which subprogram bodies and deferred constants exist.