1 Dual-V cc SRAM Class presentation for Advanced VLSIPresenter:A.Sammak Adopted from: M. Khellah,A 4.2GHz 0.3mm 2 256kb Dual-V CC SRAM Building Block in.

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Presentation transcript:

1 Dual-V cc SRAM Class presentation for Advanced VLSIPresenter:A.Sammak Adopted from: M. Khellah,A 4.2GHz 0.3mm 2 256kb Dual-V CC SRAM Building Block in 65nm CMOS(ISSCC 2006)

2Outline ●Motivation ●Dual-V CC SRAM architecture ●Chip Implementation ●Measurement results ●Summary

3Motivation ●Increase bit density in LLC ●Achieve the best energy efficiency

4 Voltage Effect on Density ●Aggressive V MIN reduces bit density

5 Dual-V CC SRAM Architecture ●Dynamic V CORE and frequency scaling ●V LLC ≈ V MAX enables smallest cell in LLC L0 to L2 cashes

6 Dual-V CC 256Kb Block ●Cut energy with stability considered ●Shifters for Timer, WL & Write drivers

7 Explicit Level Shifter Signals from mid-logic to timer: clock, RD/WR enables and sub-array selects

8 Single & Dual-V CC Word-Line Driver Static NAND gate changed to dynamic

9 Single & Dual-V CC Write Driver Static CMOS changed to Dyn-CVSL

10 Level Shifter Comparison Scheme 1 Scheme 2 This work few shiftersshifters for WL & Write drivers embedded shifters for WL & Write drivers

11 Level Shifter Comparison Embedded shifters reduce power & area this work

12 Passive Virtual Ground Clamp ●Wide V ss range due to PVT & aging programmable passive clamp sleep

13 Active Virtual Ground Clamp ●Set V REF based on standby V MIN only ●Continuously tracks PVT & aging programmable active clamp

14 Active Power Management Deactivate based on leakage

15 Active Power Management Shematic

16 Chip Micrograph 2 Dual-V CC 256Kb blocks with sleep transistor Single-V CC 256Kb block with no sleep

17 Measured Frequency and Power V LLC = 1.2V T = 85 o C 5% Activity Standby V MIN = 0.9V ●Dual-V CC block runs at GHz ●16-30mW for V CORE = V

18 Measured Leakage Power ●Leakage reduced by 30-60% for increase 2% area ●75% reduction for disabled blocks T = 25 o C T = 85 o C no retention

19 Measured Power Vs. Activity Power including dynamic overhead reduced by 23% at 1% activity -23% at 1% V LLC = 1.2V T = 85 o C V MIN = 0.9V Activity +5% at 33% -10% at 5% Total Power (mW) Without Sleep ٌ With Sleep

20 Measured Tolerance to Process Active clamp is within few mV of V MIN V LLC = 1.2V T = 85 o C 10 dies

21 Tolerance to Temperature ●Passive clamp bias set for highest T ●Active clamp saves 14-24% in leakage -14% T ( o C) V LLC -VV SS (V) active passive

22 Measured Tolerance to Voltage ●Passive clamp bias set for lowest V LLC ●Active clamp saves 24% in leakage -24%

23 Measured Tolerance to Aging Active clamp is not affected by aging Aging: Read/Write/24 hours/100MHz/1.6V/110 o C V REF = 0.3V V LLC = 1.2V

24 Dual-V CC µP Power Reduction ●35% reduction in total µP power ●Area: 3.2% cache area overhead Core64MbTotalArea Single-V CC µP µP Dual-V CC µP µP with no sleep Dual-V CC µP µP with sleep Power 1.0V Voltage V CORE = 0.7V V LLC = 1.0V

25Summary ●Dual-V CC 256Kb SRAM block in 65nm process ●Consumes 16-30mW at GHz using V CORE = 0.7V-1.2V & V LLC = 1.2V ●Embedded shifters and active clamp ●35% reduction in µP total power

26 TANK YOU