CEC 220 Digital Circuit Design Latches and Flip-Flops

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Presentation transcript:

CEC 220 Digital Circuit Design Latches and Flip-Flops Friday, March 07 CEC 220 Digital Circuit Design

CEC 220 Digital Circuit Design Lecture Outline D Flip-Flop review VHDL code for a D Flip-Flop S-R, J-K, T Flip-Flops Registers Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops Example with a Gated D-Latch Complete the timing diagram below for a gated D latch Assume that Q begins at 0 Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops An edge triggered D Flip-Flop from gated D Latches Master Slave P & Q are initially ‘0’  𝐶𝑘 P Q Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops VHDL Code for a D Flip-Flop VHDL architecture code is concurrent except for code inside a “PROCESS” statement Sensitivity list process (CLK) –- If clock changes begin if (CLK’event and CLK=‘1’) then –- Rising edge Q <= D; -- Q and QNot QN <= not D; end if; end process; Statements in here are “Sequential” Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops VHDL Code for a D Flip-Flop Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops The J-K Flip-Flop Inputs State Next State J(t) K(t) Q(t) Q(t+t) 1 Hold 1 Reset 1 Set 1 1 Toggle Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops The J-K Flip-Flop An example with the J-K Flip-Flop Assume initially Q=0 Q Set Reset Toggle Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops The Toggle Flip-Flop The T Flip-Flop Input State Next State T(t) Q(t) Q(t+t) 1 Hold 1 1 Toggle Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops The Toggle Flip-Flop An example with the T Flip-Flop Assume initially Q=0 Hold Toggle Hold Toggle Q Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops Flip-Flop Summary Hold Reset Set NA Hold Reset Set Toggle Reset Set Hold Toggle Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops Build a T Flip-Flop from a J-F Flip-Flop Excitation Table: Q Q+ S R J K T D 0 X 1 1 0 1 X 0 1 X 1 X 0 T Q Q+ 1 J K X 1 J K Friday, March 07 CEC 220 Digital Circuit Design

Latches and Flip-Flops Fill in the timing diagram for a falling-edge triggered S-R flip-flop. Assume Q begins at 0 Friday, March 07 CEC 220 Digital Circuit Design

CEC 220 Digital Circuit Design Next Lecture Shift registers Counters State Graphs Friday, March 07 CEC 220 Digital Circuit Design