1 68HC11 Timer

2 68HC11 Timer Subsystem Several timing functions: Basic timing Basic timing Real time interrupts Real time interrupts Output compare Output compare Input capture Input capture Computer Operating Properly Computer Operating Properly Pulse Accumulator Pulse Accumulator Pulse Width Modulation Pulse Width Modulation Common Features Based on a central timer Based on a central timer Overflow Flags Overflow Flags Interrupt Enables Interrupt Enables

3 Basic Timer

4 Basic Timer– TCNT $100E/0E 16-bit free running counter (timer) Cannot be set or stopped. Cannot be set or stopped. Fclk = system clock Can be prescaled by 1,4,8, or 16 Read only at memory address ($100E/$0E) Overflow flag is bit 7 in TFLG2 ($1025/$25) Overflow flag is bit 7 in TFLG2 ($1025/$25) Can use overflow to extend counter’s range Timer Overflow Interrupt Enable Timer Overflow Interrupt Enable Bit 7 in TMSK ($1024/$24)

5 TCNT - $100E:$100F Timer Counter Register Bits CNT15 READ ONLY Register CNT13CNT12CNT11CNT10CNT9CNT8 CNT CNT7 CNT5CNT4CNT3CNT2CNT1CNT0 CNT6 $100E $100F

6 Prescaler Bits PR2 PR1PAII00PAOVIRTHTOI Timer Interrupt Mask Register 2: $1024/24 -- TFLG2 PR1,PR0 = Timer prescale select - Timer Clock = System Clock / Prescale Factor Pr1 Pr0 Prescaler Timer count (overflow period) E/1 (32.77 ms) E/4 (131.1 ms) E/8 (262.1 ms) E/16 (524.3 ms)

7 Timer Overflow Flag Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) TOF = Timer overflow flag - 0 = No overflow 1 = Overflow TOF is reset to 0 by writing ‘1’ to TOF

8 Timer Overflow Interrupts Bits PR2 PR1PAII00PAOVIRTHTOI Timer Interrupt Mask Register 2: $1024 (TMSK2) TOI = Timer overflow interrupt enable 0 = disable interrupt 1 = enable interrupt

9 Basic Timer Example ************************************************* * Time delay = 1000 X ms= 524 s ************************************************* ORG $0200 SUBLDX #1000 BSET $24 $03 ; PRESCALE = ms BCLR $24 $80 ; Disable the main timer interrupt CONBSET $25 $80 : CLEAR OVERFLOW FLAG START THE TIMER MONBRCLR $25 $80 MON ; END OF INTERVAL? DEX ; NEXT INTERVAL BNE CON ; END OF COUNT? RTS ; YES, GO BACK TO MAIN PROGRAM

10 Basic Timer Example MAX_CNT Calculation Need to wait 1,000,000 or $F4240 clock cycles. Interrupt is generated every or $10000 clock cycles Max_CNT = INT(1,000,000 / 65556) = ~ 15 = $F Note: INT($F4240/$10000) = $F Note: INT($F4240/$10000) = $F Set MAX_CNT EQU $F

11 Real Time Interrupt

12 Real Time Interrupt Similar to Timer Overflow Interrupt except We have: RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) System Clock is first divided by $1000 then divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026) System Clock is first divided by $1000 then divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026)

13 Real Time Interrupt Enable Bits PR2 PR1PAII00PAOVIRTIITOI Timer Interrupt Mask Register 2: $1024 (TMSK2) RTII = Real Time Interrupt Enable 0 = disable interrupt 1 = enable interrupt

14 Real Time Interrupt Flag Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) RTIF = Real Time Interrupt flag - 1 = RTI has occurred RTIF is reset to 0 by writing ‘1’ to RTIF

15 Real Time Interrupt Prescale Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 RTR1, RTR0= Real Time Interrupt Prescale RTR1 RTR0 Nominal RTI rate (2MHz E-Clock) ms ms ms ms Port A Control Register: $1026 (PACTL)

16 Basic Timer Example ************************************************* * Time delay = 2000 X ms= 65 s ************************************************* ORG $0200 SUBLDX #2000 BSET $26 $03 ; PRESCALE = ms BCLR $24 $40; Disable the RTI TIMER interrupt CONBSET $25 $40 : CLEAR OVERFLOW FLAG START THE TIMER MONBRCLR $25 $40 MON ; END OF INTERVAL? DEX ; NEXT INTERVAL BNE CON ; END OF COUNT? RTS ; YES, GO BACK TO MAIN PROGRAM