Software Systems Division (TEC-SW) ASSERT process & toolchain Maxime Perrotin, ESA

Software Systems Division (TEC-SW) The ASSERT process in a glance

Software Systems Division (TEC-SW)  Describe the system logical architecture First, identify all functional blocks… Done at system level

Software Systems Division (TEC-SW)  Describe the system logical architecture Then connect them together …describe the messages they exchange and their non-functional attributes

Software Systems Division (TEC-SW)  Describe the system logical architecture …and let system engineers fill the blocks: they know what they want! Keep them away from software issues!

Software Systems Division (TEC-SW)  Describe the system deployment List the hardware (processors, memory, busses) Spacewire, 1553, CAN Bus… LEON2ERC32 Group the functions into partitions and map the partitions to the hardware Partition 1 Partition 2

Software Systems Division (TEC-SW)  Transform and analyze the system Analyze the system and ensure its feasibility (scheduling, safety, sizing and timing, bus load…) SYSTEM DESCRIPTION All attributes and properties are formally captured in models Generate a set of software tasks for each processor ASSERT Tool Task 1 Task 3 Task 4 Task 2 Task 1 Task 3 Task 2

Software Systems Division (TEC-SW)  Generate the software system Functional code (C, Ada) Functional code containers Tailored run-time environment 1 executable per target, ready for download

Software Systems Division (TEC-SW) In practice, how is it implemented? The system models are captured with a graphical tool that is targeted to system engineers. The Data View is captured in ASN.1 Functional blocks can be modeled using any language: SDL, SCADE, Simulink, Ada, C. Assert tools generate wrappers. Choose the best! Verification is done using existing, off-the- shelves tools (MAST+, Cheddar, AltaRica)

Software Systems Division (TEC-SW) Toolchain elements (1) Graphical front-end for assert systems –“Interface and Deployment view editors”

Software Systems Division (TEC-SW) Toolchain elements (2) Automatic “ICD” Generation

Software Systems Division (TEC-SW) Toolchain elements (3) ASN.1 Space Certifiable Compiler –Generation of compact binary encoders and decoders for ASN.1 modules –Integrated in the ASSERT tool-chain, can be used standalone as well –Targets embedded systems: no dynamic memory allocation, no system calls

Software Systems Division (TEC-SW) Toolchain elements (4) The “virtual machine” (assert VM) –First version based on the Ada runtime with the Ravenscar kernel and PolyORB-HI middleware. –Supported platforms: Leon (gnatforleon), Native (can run on top of Windows or Linux on Intel processors – without real-time) –Supported network: Ethernet (for native platforms), Spacewire (prototype only, full version within 6 months) –Ongoing: porting to RTEMS

Software Systems Division (TEC-SW) step by step demonstration 1. Make the “interface”, “deployment”, and “data” views 2. Prepare the field to implement the functions: Convert “data view” to target languages Generate application skeletons 3. Implement the functions, generate the code (don’t modify the generated code!) 4. Generate the glue code and build the system 5. Run the system

Software Systems Division (TEC-SW) application skeleton: simulink

Software Systems Division (TEC-SW) application skeleton: SDL

Software Systems Division (TEC-SW) application skeleton: C