FOUNDATION Series Software Foundation Series v1.5i Xilinx Academy Foundation Series Software Technical Marketing Spring 1999 notes pages are used with this slide show

FOUNDATION Series Software Agenda Overview and F1.5/ 1.5i/ SP1 new features Schematic-based design flow –Point-tools demonstration schematic editor, FSM editor, LogiBLOX, functional simulation –Lab: schematic entry and functional simulation HDL-based design flow –Synthesis flow demonstration HDL editor, FPGA-Express constraints editor, Express timing-tracker, pull-through implementation –Lab: synthesis and implementation; timing simulation

FOUNDATION Series Software New Features: The View At Angels One-Five* Integration with Express and Implementation Tools via API mechanisms Full Verilog Support New Look and Feel for Project Manager New Device Support –new gate simulator support for Virtex –4KEX/XL/etc. merged into “4000X” symbol library –XC9500XL –SpartanXL *that means 15,000 feet - reference: “The Final Cut”, Pink Floyd, (This may be a quiz question…) F1.5 F1.5

FOUNDATION Series Software Foundation Releases F1.5 (out in 9/98) F1.5i (since 11/98) –Top-level schematic in HDL flow –Express –Bug fixes F1.5i Service Pack 1 (2/99) –Express 3.1 –Virtex functionality fixes F1.5i Service Pack 2 (3 or 4/99) –Xilinx implementation update

FOUNDATION Series Software Project Manager As of F1.5, PCM is now truly “Mission Control” for Foundation –Express GUI and Design Manager are no longer required in most cases –These are still provided in “Xilinx Foundation Series > Accessories” folder Menus organized for ease of use and support of integrated synthesis and implementation functionality F1.5 F1.5

FOUNDATION Series Software The Concept of Project Flows (Subtypes) Necessitated by the introduction of FPGA Express integration and HDL-centric flow Two Flows: HDL and Schematic –Schematic: very similar to F1.4 Projects –HDL: Express-centric; entire design processed by Express (except black box instantiations) Cannot be changed after project creation F1.5 F1.5

FOUNDATION Series Software Flow Diagram “Phase Box” Design Step Grouping –Some phases contain individual tool buttons Flow Automation implemented here Flow Progress Indicators Flow-sensitive Diagram Layout –Schematic Flow’s diagram does not have Synthesis Phase “Pull Model” Automation Single-action Phase button Multiple tool Phase button

FOUNDATION Series Software Verilog & VHDL Instantiation VHDL ABEL FPGA Express XNF LogiBLOX Module Generator HDL Editor State Diagram Editor Symbol Generation Schematic Design Tools Command File or Test Vectors Unified simprim Simulation Tools BIT JEDEC EDIF Reports SDF VHDL Verilog Implementation Tools EDIF Foundation Series Training Lab Flow Diagram: point tools training

FOUNDATION Series Software Schematic Design Tools Schematic Editor –Well integrated with simulator –Graphical GUIs –ViewLogic importing CORE Generator / Logiblox Integration –Same functionality as standalone tools State Diagram Design Entry –Simplifies FSM generation Symbol Wizard –Macro symbols and port definitions F1.5 F1.5

FOUNDATION Series Software Functional Simulation Easy Stimulus generation keyboard toggling, simple clock stimulus, custom formulas Easy Debugging waveform viewer, easy to add and remove signals, correlated to schematic editor Script Editor supports Viewlogic and Aldec command file syntax New Simulation Script Wizard easy simulation command files generation Memory allocation tuning to support larger netlists

FOUNDATION Series Software Begin Labs

FOUNDATION Series Software HDL-flow Agenda Pull-through to implementation Synthesis features, and differences between HDL flow projects and schematic flow Versions and Revisions Demo: HDL editor, error-navigation, pull- through to implementation, versions/revisions. Lab Advanced synthesis features, F1.5 issues

FOUNDATION Series Software HDL Project Flow Supported only in BSX and EXP configurations Synthesis always initiated from PCM (not from HDL Editor/FSM as it is in Schematic Flow) ABEL not supported except as black-box instantiation Before synthesisAfter synthesis (this dialog will show the last synthesized target) “File > Project Type” Dialogs

FOUNDATION Series Software Synthesis Options Dialog FSM Encoding Style One Hot Binary FSM Extraction Method Safest (all possible states) Smallest (defined states only) Direct export timing constraints to implementation tools Set default target clock constraint Synthesis options should be set before files are analyzed.

FOUNDATION Series Software “Pull” Model Implemented for Synthesis, Functional Simulation, and Implementation Phase Boxes Design will be “pulled through” the required processing steps to bring it to point that user selects –Filling out “Synthesis/Implementation” Dialog is required for 1st-time run

FOUNDATION Series Software Synthesis/Implementation Dialog This dialog is used for both Synthesis and Implementation Phase Invoked from Files or Versions tab, from the Synthesis or Implementation pull-down menus, or as a result of selecting the Synthesis, Simulation, or Implementation Phase boxes Depending on how invoked, one section or the other may be grayed out Note that “assertion level” of Express Constraint Manager and Timing Tracker are opposite of those in the standalone Express GUI

FOUNDATION Series Software Files Tab (HDL Flow) HDL files’ entities shown via Express API Status of each HDL file’s Analysis shown Local Menus provide Power User functions

FOUNDATION Series Software Versions Tab - HDL Flow Project Displays both Express Elaborated/Optimized Structures and Xilinx Versions/Revisions Symbols (“ X,” “ !,” “ ? ”) indicate elaboration/optimization results Local menu pick for FE.LOG Interactive Flow Engine can be invoked on any Revision at any time

FOUNDATION Series Software Versions Tab for Schematic Flow Top-level object corresponds to “xproj” directory Target family determined by File>Project Type dialog setting (as it was in F1.4) Changing Project Type will attach new Unified Library to Project; subsequent Implementations will use the new Family

FOUNDATION Series Software FPGA Express Constraints Editor Define Clocks PERIOD / RISE / FALL Define Time Constraint FROM : TO Sub-Paths Define Port Attributes DELAY PULLUP / PULLDOWN SLEW / Global Buffers Pin Locations Define Hierarchy Preservation Eliminate / Preserve Operator Sharing Optimize / Effort Xilinx Constraints Implementation Tool Target GSR Usage

FOUNDATION Series Software Types of Constraints used by Express Constraints that can be applied from the Express Constraints Editor: –FROM:TO timespecs which use FFS, LATCHES, and PADS –User Defined Sub-Paths –Control Use of IOB Register –Pin Location Constraints (LOC) –Slew Rate –Pull-up / Pull-down –Input Register Delay

FOUNDATION Series Software Timing Analysis Time-Tracker tm Path Delay Instance Fanout Timing Constraint Estimated Timing

FOUNDATION Series Software HDL Design Tools CORE Generator / Logiblox Integration State Diagram Design Entry –Simplifies FSM generation HDL Design Wizard –Accelerates design creation HDL Editor with Integrated Language Assistant - VHDL and Verilog –Color coding simplifies design entry & analysis –Efficient pre-designed HDL functions speed design F1.5 F1.5

FOUNDATION Series Software Messages/Reports Express GUI tabs implemented in Console area Xilinx Report Browser available via Reports Tab “Implementation Log File” (FE.LOG) also shown

FOUNDATION Series Software Begin Labs

FOUNDATION Series Software GSR insertion during synthesis Express automatically detects the presence of set / reset signals in the design –A net that sets / resets all sequential elements in the design –A net driven by a GSR cell (STARTUP) Merges / Resolves GSR nets if more than one exists Inserts STARTUP symbol into netlist, if needed (and if appropriate for the architecture) Includes Black Boxes if instructed by user in Modules tab of constraints editor

FOUNDATION Series Software Automatic I/O Buffer Mapping Selectable Per I/O Default is TRUE TRUE Invalidates MAP -pr Switch DQ FD OBUF OPAD IOB DQ OFD

FOUNDATION Series Software Optimization Options Recommended Defaults –Area / High For CPLD –Speed / High for FPGA –Eliminate Hierarchy –Preserve Primitives Customize Optimization Per Module

FOUNDATION Series Software Optimization Options... Primitives Controls optimization of netlist primitives May still optimize basic primitives (AND, OR, etc) XNF, VHDL, Verilog netlist RTL PreserveEliminate

FOUNDATION Series Software Optimization Options... Hierarchy –Controls how many XNF files are written –May leave some logic which could be optimized across boundary PreserveEliminate

FOUNDATION Series Software F1.5i and SP1 Licenses Express uses FlexLM license –Users with valid F1.4/1.5 license need only update existing license’s PACKAGE stmt –Install program copies FND-BSX-PC license ( Load & Go ) for evaluation register limit: 2100 registers (largest Spartan part) Express constraint editor GUI is not available with BSX license expires January 2000? No license necessary for Foundation tools

FOUNDATION Series Software Migration of F1.4 Designs Into F1.5 No automatic conversion is done –F1.4, XACT 6 Projects opened in their native Project Type (but note that Xilinx does not have SQA resources to test these old flows) Conversion is one-way Automatic determination of proper Flow (Schematic or HDL) Customers with existing designs that contain X-VHDL (Metamor) blocks may wish to keep Metamor installed for support of those designs –Metamor can be installed as a standalone component from the F1.4 Design Entry Tools CD

FOUNDATION Series Software Where to find HELP! Issues are documented in several places –Hotsheet (“Read Me First” document in the box) –Release document –Answers Book –Solutions Database –Foundation Expert Journal Sources for learning and training –Foundation Quick Start guide (hard copy, DynaText) –Foundation User’s Guide (DynaText only) –Foundation On-Line Help

FOUNDATION Series Software the end.

FOUNDATION Series Software Appendix the following slides and notes are included for reference

FOUNDATION Series Software Solution Records to be aware of Solutions are available at: (where XXXX is the 4-digit solution number) Solution selecting optimal options for synthesis Solution migrating libraries from F1.4 (Metamor) to F1.5 (Express) synthesis, when using FSM editor Solution clarification of version/revision control Solution HDL tutorial in quick start guide needs GSRT manual toggle added to simulation Solution Message window appears behind project manager, PCM appears to hang

FOUNDATION Series Software Behavior of Programming Phase Box CPLDs: JTAG Programmer invoked FPGAs: Tool selector dialog invoked –Architecture context-sensitive –F1.5i will add JTAG Programmer selection for applicable FPGAs

FOUNDATION Series Software What’s New With Express Express 3.1: schematic viewer available in stand-alone mode (SP1) New architecture support (2.1.3) –Virtex Addition of some VHDL ‘93 constructs –end keyword-component keyword –is keyword-labels on assignments –T’image(X)-block in generate –alias keyword-array slices with others Addition of other HDL constructs –rising_edge / falling_edge –‘else –hex, octal and binary for std_logic_vectors

FOUNDATION Series Software “Synthesis” and “Implementation” Pull-down Menus Synthesis Menu Provides Design- Global Functions Plus a Few “Expected” Items “local” functions are provided via local (right-mouse-button) menus Shown in HDL Flow only Implementation Menu Provides: –Duplicates Implementation Phase Button and “Implement” local menu pick –Invokes Xilinx Report Browser –Invokes Project Options dialog

FOUNDATION Series Software Express Integration (F1.4 to F1.5) Emulation of Express look and feel in Files tab and Versions tab –Local menus –Files tab source status markers (check mark, ?, X) –Files tab entities display –Versions tab Functional/Optimized Structure and entities display However, some changes consciously made to improve usability –Example: some changes in local menus –Example: dialog box option “assertion levels” (I.e. “Do not insert I/O pads” changed to “insert I/O pads”) Full Constraint Manager and Timing Tracker implementation

FOUNDATION Series Software Constraint Editor Synopsys Constraint Editor –Used for HDL flow –Synthesis and Implementation Constraints –No TIG, TIMEGRP, TPTHRU Xilinx Constraint Editor –Used for Schematic flows –Requires NGD file –No synthesis constraints

FOUNDATION Series Software Useful Features To Be Aware Of Project Manager: selectable fonts for panes, Console areas Simulator: Print Current Page, Print Time Region (F1.4) Simulator: Graphical Waveform Editing via Local Menu “Edit” Function (F1.4) HDL Editor: Insert File Simulator: Macro Assistant, Macro Wizard Synthesis: Encoding Style option

FOUNDATION Series Software Joint Marketing Agreement Tools JMA partners’ behavioral simulation tools Evaluation copies included in F1.5 box (BSX, EXP configurations only) –Model Technology’s ModelSim stand-aside tool. VHDL and Verilog simulation –Aldec’s ACTIVE-VHDL “known” by PCM. Design automatically exported when ACTIVE-VHDL selected from Tools menu. VHDL simulation