System-on-Chip Design Homework Solutions Hao Zheng Comp Sci & Eng U of South Florida

HW 2

P2.1 The values of tokens into the snk actor is 2, 4, 6, …, i.e., Figure 2.24 The values of tokens into the snk actor is 2, 4, 6, …, i.e.,

P2.2 Fibonacci Sequence Figure 2.24

P2.3: Original SDF

P2.3: Transformed SDF snk2 fork fork add fork 1

P2.4: Accumulator with Adder src add

P2.5 The topology matrix Figure 2.26 For PASS to exist, the rank must be 2. Set X = 2 and Y = 1, then the combination of first two columns gives the third one.

HW 1

P1: Structural Models at System and Processor Levels

P1: Structural Models at System and Processor Levels

P2: why a system-level structural model is more abstract than a processor- level structural model? Each component in a system-level structural model represents a design at the processor-level, which can be in many various forms such as a behavioral model, structural model as shown before, or a different structural model, etc. Implementation of communications over buses are defined in terms of messages, not bits.

P2: why a system-level structural model is more abstract than a processor- level structural model? Components in a processor-level structural model are described at the more detailed register-transfer cycle accurate level. Component interfaces and buses are bit-accurate and

P3: differences between the behavioral models at the cycle-accurate level and the instruction level. In a cycle-accurate model, the design behavior captures how registers are updated on individual clock edges. Each instruction typically takes a number of cycles to execution. An instruction accurate model captures how memory/registers are updated after execution of each individual instructions.

P4: benefits of using instruction accurate models compared to cycle-accurate models Each instruction typically takes a number of cycles to execution. An instruction accurate model captures how memory/registers are updated after execution of each individual instructions, without considering the register updates at each cycle. Therefore, simulating instruction accurate model is much faster. Allows early development and validation of SW.

P4: benefits of using transaction-level models compared to instruction accurate models Each transaction represents a sequence of instructions, ex. printf() Simulating transaction accurate model is much faster. Important for early exploration of system design space. Provide a function-accurate system prototype for early development and evaluation of SW.

P5 What is the system level synthesis? A process that converts a system behavioral model to a system-level structural model.

P5 What is the input model to the synthesis like?

P5 What are the key elements in the generated models? Processing elements such as CPUs, DSPs, memory controller, buses, communication/peripheral interfaces, custom HW logic components, etc.

P6(a) What would the design model look like if the system behavioral model is implemented in software completely? CPU DSP

P6(b) What would the design model look like if the system behavioral model is implemented in hardware completely? HW/ASIC HW/ASIC HW/ASIC

P7 pros and cons of pure software or pure hardware implementations for a given system. Fig. 1.6 Driving factors in HW/SW co-design

P8 Differences between concurrency and parallelism Concurrency is the ability to execute simultaneous operations because these operations are completely independent. Related to behavior of applications. Parallelism is the ability to execute simultaneous operations because the operations can run on different processors or circuit elements. Related to HW implementations.