NTUEENTUEE 1 Introduction to Cadence 講員：張祐齊 日期： 原講員：魏睿民

NTUEENTUEE 2 Outline Setup the environment Starting Cadence Using layout editor Extract layout to spice Using Timemill

NTUEENTUEE 3 Environment Setup Making a directory for using cadence, such as cad. Specify cds.lib in your working directory. –The easier way is copy mine to your directory like this, cp ~r89052/cad/cds.lib your_directory Type icfb& to running cadence in background.

NTUEENTUEE 4 Def. Of Some Files Technology file ( 035.tf ): specifies all the tech.-dependent parameters associated with that particular library. divaDRC.rul, divaEXT.rul, divaLVS.rul are design rules for DIVA tools. They provide on-line rule-check in layout editor. display.drf is a file containing layer display information. cds.lib is a file containing library definition..cdsinit skill format, pre-define the bindkeys, skill search path, text editor..simrc skill format, set simulation and netlisting environment variable

NTUEENTUEE 5 Create a New Library File => New => Library Your library name Choose this Tech. file

NTUEENTUEE 6 Create a New Library After creating a new library directory,we still need to copy some files below in the library directory: divaDRC.rul divaLVS.rul divaEXT.rul divaERC.rul display.drf

NTUEENTUEE 7 Create a New Cell File=> New => Cell Your library name Choose Virtuso for layout view, Schematic for schematic view Specify your cell name

NTUEENTUEE 8 Open Layout Editor File => Open … Choose Library Choose Layout view Choose Cell

NTUEENTUEE 9 Layout Editor Present point Relative point present command LSW Bar click middle button

NTUEENTUEE 10 Physical Layout Techniques Once a circuit design is complete, it becomes necessary to provide an area-efficient layout of the circuit to generate the masks necessary for fabrication. We must define the following: ”NWELL”, “PWELL”, “THIN”, “GPOLY”, “CONT”, “METAL1”, “METAL2”, “METAL3”, “VIA1”, “VIA2”, “NPIMP”, “PPIMP” in the layout database for 0.35μm TSMC process of CIC.

NTUEENTUEE 11 Physical Layout Techniques

NTUEENTUEE 12 Physical Layout Techniques The n+ diffusion can be defined by “NPIMP” and “THIN”. With poly across, a NMOS is formed. The p+ diffusion can be defined by “PPIMP” and “THIN”. With poly across, a PMOS is formed. Also PMOS is formed on “NWELL”. Conductor: Poly and metals. They are in different layer and disconnected unless through “CONT” or “VIA”. “CONT” is for poly and metal1. “VIA” is used between 2 metals. There is also “THIN” at “vdd!” And “gnd!”, “CONT” is required to connect “THIN” and “Metal1”. Once the “THIN” exist, there is PPIMP or NPIMP. After finish drawing, do not forget to place pins on inputs and outputs.

NTUEENTUEE 13 Useful Hotkeys Some useful hotkeys: –r: draw rectangular block –z/Z: room in and room out –k/K: ruler on/off –s:stretch –c: copy m: move u: undo Del: delete q:query p: create path

NTUEENTUEE 14 LSW

NTUEENTUEE 15 Option->Display

NTUEENTUEE 16 Options->Editor

NTUEENTUEE 17 On-line DRC

NTUEENTUEE 18 HW1 (1) 請用 CADENCE 畫出 transmission-gate full adder 的 Layout 。 (2) 此 Layout 必須通過 ON-LINE DRC check (3) Due on March 13

NTUEENTUEE 19 Open the extracted view and type shift-f, we can see the N/PMOS with the value of L/W. Select Cparasitics Getting Extracted View

NTUEENTUEE 20 Extract Layout to Spice (I) For the analog artist, do the following 3 steps: 1.Open.cshrc and find the line: setenv CDS_Netlisting_Mode=Digital change “ Digital ” to “ Analog ” 2.Open.simrc and find the line: simNlpGlobalLibName=sample change “sample” to “analogLib” 3.In divaExt.rul, change the capacitor model to “pcapacitor” change the transistor model to “pmos4” and “nmos4”.

NTUEENTUEE 21 Extract Layout to Spice (II) For the digital artist, do the following 3 steps: 1.Open.cshrc and find the line: setenv CDS_Netlisting_Mode=Analog change “ Analog ” to “ Digital ” 2.Open.simrc and find the line: simNlpGlobalLibName=analogLib change “analogLib” to “sample” 3.In divaExt.rul, change the capacitor model to “capacitor” change the transistor model to “pfet” and “nfet”.

NTUEENTUEE 22 CDL OUT – step1

NTUEENTUEE 23 CDL OUT – step 2 本例中輸出檔案為 an2.sp

NTUEENTUEE 24 Preparation to Run TimeMill The files required to run TimeMill –*.sp: your spice file –*.cfg: 設定電源電壓及欲觀察的節點 –*.io: 設定 test pattern 的輸入檔案及 IO pin name –*.vec: 設定測試 pattern –*.ctl: control file –Ls35_4_1.l: TSMC spice model * 表示待測試電路的名稱，如果是 circuit 是 an4 ，則 *=an4 這些檔案都可以從網頁上抓到，在接下來的範例中以 an2 cell 為例。 執行檔： –spice2erun –printwlrun –gentechrun –timerun

NTUEENTUEE 25 Running TimeMill – step 1 透過 spice2e 將 an2 轉成 an2.ntl （ EPIC 檔案格式） – 將 an2.sp, spice2erun 拷貝至工作站下同一目錄 – 將 spice2erun 的屬性更改為可執行並執行 " spice2erun 內容，共三行 " –echo "spice2e running!" –spice2e -i an2.sp -o an2.ntl -f hspice -1 –echo "spice2e end!" 輸出檔案 an2.ntl 注意： mos 的長寬都要改成以 u 來表示。如 l=3.5e-7 要改成 l=0.35u 。

NTUEENTUEE 26 Running TimeMill – step 2 透過 printwl ，根據 an2.ntl 產生 an2.wl1 – 將 an2.ntl, printwlrun 拷貝至工作站下同一目錄 – 將 printwlrun 的屬性更改為可執行並執行 " printwlrun 內容，共三行 " –echo "printWL running!" –printWL -n an2.ntl -m AN2 -o an2.wl –echo "printWL end!“ -m 後面是接 spice 檔中 subckt 的名稱

NTUEENTUEE 27 Running TimeMill – step 3 根據 an2.wl1 產生新的 an2.ctl “ an2.wl1 內容，共八行 ” –%model –.model n nmos –.model p pmos –%parameters –N_LENGTH –NW –P_LENGTH –PW 將 an2.wl1 整段複製到 an2.ctl 相對的地方

NTUEENTUEE 28 Running TimeMill – step 4 透過 gentech 產生 an2.tech – 將 an2.ctl, ls35_4_1.l, gentechrun 拷貝至工作站下同一目錄 – 將 gentechrun 的屬性更改為可執行並執行 " gentechrun 內容，共三行 " –echo "begin: `date`" –gentech -c an2.ctl -t an2.tech -f hspice -m -q –echo "end: `date`“ 輸出檔案是 an2.tech

NTUEENTUEE 29 Running TimeMill – step 5 進行 timemill 模擬 – 將 an2.ntl, an2.io, an2.cfg, an2.tech, timerun – 拷貝至工作站下同一目錄 – 將 timerun 的屬性更改為可執行並執行 " timerun 內容，共三行 " –echo "run timemill" –timemill -n an2.ntl an2.io -m AN2 -o an2 -c an2.cfg -p an2.tech -d t -t 50 –echo "end timemill" 50 是模擬的時間長度，跟 test pattern 長度有關

NTUEENTUEE 30 Running TimeMill – step 5 注意事項：將 an2.ntl 的 n 改成 nch “an2.io” (is=vec)(en=an2.vec)(ot=A,B); “an2.vec” ;AB radix11 ioii 輸出檔案 : an2.out

NTUEENTUEE 31 Running TimeMill – step 6 Debussy 1. 看波形

NTUEENTUEE 32 Running TimeMill – step 6 2. 選擇輸入檔案 5. 選擇節點

NTUEENTUEE 33 Running TimeMill – step 6 3. 將檔案格式選 成 *.out 4. 選擇所要觀 察的 ckt

NTUEENTUEE 34 Running TimeMill – step 6 6. 選擇觀察節點 7. 得到結果