CEC 220 Digital Circuit Design State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Slide 1 of 13.

Slides:

Advertisements

Similar presentations

Chapter #8: Finite State Machine Design 8

Advertisements

1ASM Algorithmic State Machines (ASM) part 1. ASM2 Algorithmic State Machine (ASM) ‏ Our design methodologies do not scale well to real-world problems.

IN2305-II Embedded Programming Lecture 2: Digital Logic.

TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.

Give qualifications of instructors: DAP

FIGURES FOR CHAPTER 19 STATE MACHINE DESIGN WITH SM CHARTS

Nonlinear & Neural Networks LAB. CHAPTER 19 State Machine Design with SM charts 19.1 State Machine Charts 19.2 Derivation of SM Charts 19.3 Realization.

CS 151 Digital Systems Design Lecture 37 Register Transfer Level

ECE 331 – Digital System Design State Reduction and State Assignment (Lecture #22) The slides included herein were taken from the materials accompanying.

ECE 331 – Digital System Design

3/20/20091 More State Machines. Multiple processes.

10/20/20081 Lab 6 – More State Machines. Multiple processes.

10/13/ Lab 6 - Algorithmic State Machines ECE238L 10/13/2009.

3/13/20081 Lab 6 Solution Part 1: Design a sequence detector for the sequence “00101” Part 2: a b See sm1.vhdSee sm2.vhd See seq1.vhd.

Algorithmic State Machine (ASM) Charts

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,

SM Charts and Microprogramming

ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)

ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

CSE 311: Foundations of Computing Fall 2014 Lecture 23: State Minimization, NFAs.

State Machines.

FINITE STATE MACHINES - II

CprE / ComS 583 Reconfigurable Computing

George Mason University Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code ECE 448 Lecture 6.

Lecture 9 RTL Design Methodology. Structure of a Typical Digital System Datapath (Execution Unit) Controller (Control Unit) Data Inputs Data Outputs Control.

CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Friday, February 14 CEC 220 Digital Circuit Design Slide 1 of 18.

Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 1 Digital Fundamentals.

CEC 220 Digital Circuit Design Timing Analysis of State Machines

CEC 220 Digital Circuit Design Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Slide 1 of 19.

CEC 220 Digital Circuit Design VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Slide 1 of 13.

CEC 220 Digital Circuit Design Counters Using S-R and J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Slide 1 of 19.

CEC 220 Digital Circuit Design Sequence Detector Design Wednesday, April 01 CEC 220 Digital Circuit Design Slide 1 of 11.

CEC 220 Digital Circuit Design Programmable Logic Devices

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Basics of register-transfer design: –data paths and controllers; –ASM.

CEC 220 Digital Circuit Design Dice Game Wed, April 06 CEC 220 Digital Circuit Design Slide 1 of 15.

CEC 220 Digital Circuit Design Mealy and Moore State Machines Friday, March 27 CEC 220 Digital Circuit Design Slide 1 of 16.

CEC 220 Digital Circuit Design More Karnaugh Maps Monday, February 02 CEC 220 Digital Circuit Design Slide 1 of 11.

ECE 301 – Digital Electronics Logic Circuit Design (Lecture #9)

Midterm Exam ReviewCopyright Joanne DeGroat, ECE, OSU1 Midterm Exam Notes.

Introduction ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

1 ECE 545 – Introduction to VHDL Algorithmic State Machines Sorting Example ECE 656 Lecture 8.

CEC 220 Digital Circuit Design SOP and POS forms Friday, January 23 CEC 220 Digital Circuit Design Slide 1 of 17.

ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.

ECE DIGITAL LOGIC LECTURE 21: FINITE STATE MACHINE Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 11/24/2015.

ASM Charts. Outline  ASM Charts Components of ASM Charts ASM Charts: An Example  Register Operations  Timing in ASM Charts  ASM Charts => Digital.

CEC 220 Digital Circuit Design Latches and Flip-Flops

ASM block The state box represents the state in the FSM, and the output in the state box describes the desired output values when the FMS enters this state.

CEC 220 Digital Circuit Design SOP and POS forms Friday, Sept 11 CEC 220 Digital Circuit Design Slide 1 of 17.

1 강의노트 09 Logic Design with ASM Charts: Based on Digital Systems Design Using VHDL, Chapter 5, by Charles H. Roth, Jr.

Digital Design with SM Charts

Partitioning of a digital system.

Lecture 1 Gunjeet kaur Dronacharya group of institutions.

Algorithmic State Machine (ASM) Charts: VHDL Code & Timing Diagrams

State Machine Design with an HDL

George Mason University Finite State Machines Refresher ECE 545 Lecture 11.

Partitioning of a digital system.

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code.

IAY 0600 Digital Systems Design

ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.

Digital Principles and Design Algorithmic State Machines

ECE 434 Advanced Digital System L13

Synthesis of sequential circuits

Table 8.1 Verilog 2001 HDL Operators

Instructor: Alexander Stoytchev

IAS 0600 Digital Systems Design

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code.

RTL Design Methodology Transition from Pseudocode & Interface

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.

Lecture 17 State Machine Design Using SM Chart

ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.

Presentation transcript:

CEC 220 Digital Circuit Design State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Slide 1 of 13

Lecture Outline Friday, April 11 CEC 220 Digital Circuit Design State Machine Charts  Describing state machines using state charts Implementing a State Machine in VHDL Slide 2 of 13

State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design State Machine (SM) Charts  An alternative to state transition graphs and state transition tables State Box Decision Box Conditional Output Box The three principal components of a SM chart Slide 3 of 13

State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design The State Machine Block One entrance path Many exit paths Decision boxes Conditional Output boxes (Mealy) One SM block for each state Each SM block is typically NOT unique Slide 4 of 13

State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design SM blocks are typically NOT unique Pres. State Next StatePres. Output (Z 1 Z 2 ) S1  Pres. State Next StatePres. Output (Z 1 Z 2 ) S1S2S3S2S  Pres. State Next StatePres. Output (Z 1 Z 2 ) S1  Pres. State Next StatePres. Output (Z 1 Z 2 ) S1S2S3S2S  Slide 5 of 13

State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Another example of equivalent SM’s Slide 6 of 13 Multiple active link paths Single active link path

State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Conversion of a State Graph to a SM Chart Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S0 S1 S2 Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S0100?? S1010?? S2001?? Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S S S Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S0 S S1S0S S2S0S Slide 7 of 13

State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Examples: Convert the State Graphs to SM Charts Slide 8 of 13

Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design State Machine Implementation in VHDL Pres. State Next StatePres. Output (Z) X=0X=1 S0 = 000S2S10 S1 = 001S5S00 S2 = 010S3S10 S3 = 011S3S40 S4 = 100S4S31 S5 = 101S4S00 Slide 9 of 13

Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design Define the next state behavior here!! Slide 10 of 13

Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design SM in VHDL Slide 11 of 13

Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design Simulation Waveform  VHDL code is online Slide 12 of 13

Next Lecture Friday, April 11 CEC 220 Digital Circuit Design A Digital Design Example  Dice game design Slide 13 of 13