M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June Status of the PINT chip M. Adinolfi University of Oxford

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June L0 Interface Board Block Diagram JTAG PINT /MINT DataControls G-Link (GOL) Parallel/serial Fibre Driver VCSEL Data + Headers (BX, Parity, CRC) ECS Receiver To L1 Fibre Receiver SFF-LC Connector TTCrx From TTCvi IIC JTAG Configuration & Monitor To ECS (JTAG)

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June The L0 prototype GOLs PINT

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June PINT  MINT  The different non analogue readout schemes have no major impact on the data transmission to the Level-1 Board.  The output signals (Control signals for the GOL - data format - parity checks - CRC - headers and trailers) are essentially unchanged.  Data input from Beetle and/or ADC is of course different but does not represent a major change.  Modifications to the interface with ECS, JTAG  IIC conversion for TTCrx etc. should not be needed.  Analogue read-out: most of the current work is useless.

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June Aim of current tests As the current electronics chain does not require major changes In any non-analogue scenario, using the prototype for the pixel chip it is possible to test:  Interfacing with the TTCrx;  Interfacing with the GOL;  PINT/MINT algorithm;  Data format & error correction schemes;  Data transmission to L1 board, including clock jitter effects, transmission errors measurement etc.

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June The story so far  Level-0 board delivered and tested in May - see Laura presentation at the last LHCb week.  Several weeks lost trying to understand the JTAG interface: Attempt to write a custom program to load the Spartan configuration failed (at least for now). GOL clock: The JTAG state machine of the GOL uses the internal clock rather than the JTAG clock to load the registers. The internal clocks slows down till stop if no external clock is provided. The PINT provides the external clock to the GOL. The TTCrx on the L0 board is not recognized by the Xilinx JTAG software. Some “bricolage” on the board has been needed.  PINT configuration successfully loaded on Friday

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June Sample signals from the PINT Pixel control signals Gol control signals Data Row Parity

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June The PINT today Using the signals available on the TEST connector is it possible to see:  The PINT provides the clock to the GOL which successfully locks.  The L0 triggers signals are received and the corresponding control signals to the PIXEL chip are generated.  The control signals for the GOL, marking the START and the END of each event are correctly generated. Nevertheless further tests are needed to gain 100% confidence in the PINT.

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June A glance at the near future  Further tests are needed to verify the PINT algorithms, the data formatting, and the BX Id FIFO. As this has been already studied using the Spartan test board no major problem is foreseen.  The PINT internal pattern generator can then be used to transmit data to the GOL and from there to the L1 electronics. It will thus be possible to investigate the data transmission, measure error rate, effects of the clock jitter etc.  Finally the whole L0  L1  DAQ chain can be verified.  The ultimate goal is to prove the design is capable of transferring binary/digital data from the selected photo-detector to the DAQ.

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June Conclusions A design is available for the L0 electronics to read-out binary/digital data from the selected photo-detector. The designed is based on a FPGA to provide the control logic on the board, the GOL and the VICSEL to drive the data through optical links to the L1 electronics in the counting room. First tests show that in the 1 st prototype of the front-end board, the FPGA behaves as expected, though further tests will be performed next week to gain 100% confidence. The data transmission scheme will be then validated. Time scale for the validation is of the order of 4-6 weeks. This does not include summer holidays, attendance to meetings etc.