SPP FIELDS DFB Quarterly Feb 23, 2015 Solar Probe Plus FIELDS Instrument Quarterly Digital Fields Board (DFB) 1

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Development Status (1of2) Q Completed initial EM2 testing, including linearity and signal integrity –Results in review, further testing after MEP environmental tests Completed thermal testing of the ProtoRTAX FPGA DB with EM2 –Testing requested to determine power draw for FIELDs instrument resource assessment Results indicate FPGA power draw within linear region of predicted power curve (no runaway current condition exhibited) Tests provide confidence in CBE power for FIELDS (further thermal performance measurements to be made on other FIELDS FPGAs in 2015) Built two additional Xilinx DBs due to manufacturing issues –BGA attachment and DB to main board connector seating Modified EMI shield to account for component height on a memory part –Implemented on EM2 and planned for FM (photos in presentation backup materials) –Modification approach to be used on DCB Continued FPGA modules lab test validation –Focus on Digital Burst Memory with simulations and lab testing Retired SIDECAR CGA attachment risk with completion of DFB vibration test Lowered ASIC workmanship risk with completion of more testing on both EMs and thermal cycling of EM2 Completed DFB Pre-CDR Peer Review Dec 3 rd, actions closed Supported Fields I-CDR, supporting action close-out 2

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Development Status (2of2) Q Completed play-date with SCM Feb using EM1 –Testing went well, results in review Integrated EM2 with Xilinx DB in MEP Feb 19 –Xilinx DB to be used for MEP I&T, EMI testing, and TVAC –ProtoRTAX DB included in this delivery to SSL for Vibe tests later in Spring –EM1 to be at LASP for continued development and test of EM and FPGA Submitted EEE part stress/de-rating analysis for project review/concurrence –No identified concerns with parts analysis Revisited FPGA DB CGA analysis to verify margins, with known assumptions, margins sufficient to survive launch loads (details in backup slides) Adjusted Digital Burst Memory FPGA module architecture due to completion delays Continued debug and test of FPGA code Completed pre-flight DFB default mode definition and configuration space that would be most likely exercised in flight Worked with SSL SOC to resolve survey waveform data rate issue Initiated conversations with SWEAP team about 'figure of merit' in support of DFB burst captures 3

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Financial Assessment Q DFB has maintained overall 533 budget and EVM EVM spend-plan updated and correlated to schedule and budget –Plan maintains total costs at baseline levels with some adjustments to EM and FM WBSs reflecting current and future expenditures –Parts and respective costs have been transferred from EM to FM WBS –EM EAC reduced due to parts transfer –FM EAC projected slightly over due to extended FM schedule tasks –Science, Systems I&T, and LOE restored to proposed budget values, and projected to meet EV EAC Budget (533) EAC correlated to EVM spend-plan –533 overall maintained within budget and projected EAC –Small amount of encumbrances for travel, ODC, and some material costs 4

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Staffing Plans Q Staffing profile submitted to project As planned, Vaughn Hoxie moved off DFB at I-CDR –Tasks completed or transitioned to other DFB team members –Vaughn is available as needed to support on-going development Added Ken Stevens in Oct to assist with delays in FPGA development –Ken is a contractor, a prior LASP employee, and a prior DFB FPGA designer for THEMIS, MMS, and Van Allen Probes –Ken is full time thru June, and may stay involved at LASP on other project(s) Magnus Karlsson is moving to another project at end to Feb –Ken to pickup any remain tasks from Magnus and work with Summers and Malaspina on FPGA completion and moving into regression testing All other staffing remains the same 5

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Schedule Q Supporting MEP I&T with EM2 Further testing using EM1 Focused FPGA DBM module development

SPP FIELDS DFB Quarterly Feb 23, 2015 If the SIDECAR experiences latent failure and/or has reliability issues, then the lack of a complete EIDP and respective workmanship could hinder the debug/troubleshooting, and have the potential to degrade performance and warrant possible redesign which could increase needed mass and power. Risk mitigation plan is to perform characterization and environmental testing on the SIDECARs. These parts have prior electrical burn-in testing hence characterization and environmental tests will demonstrate good rigor to retire the risk. Risk rating: Probability lowered from 2 to 1, Impact 3; not likely to occur based on successful burn-in testing completed by GSFC/Teledyne; and recently completed thermal testing. Consequences slightly higher based on possibility of reverting to backup plan of discrete ADCs. Proposed/heritage ADCs are not as rad-tolerant, require more board space (mass increases), more power, and/or could drive science return. Newer, more viable, ADCs identified but require radiation testing. DFB Risk Mitigation Progressing SPF-DFB01 IDTITLEPICritImpactTrendRetire At SPF- DFB01SIDECAR workmanship13 L PM Screening Complete, thermal testing and continued operation of SIDECAR in both EMs reflect robustness; risk probability lower SPF- DFB02PWB Structural Deflection23 L PMSC Post PDR vibration testing Complete, Q results satisfactory If the DFB PWBA experiences too high of structural deflection, then the assembled components may experience package stresses, with respective workmanship and/or reliability issues. The primary concern is the SIDECAR CGAs. This potential could warrant possible redesign of the PWB layout, structural stiffness design, or reduction in DFB capability due to replacing the SIDECAR/other components to stay within mass and power constraints. Analysis and part modeling in process now. Risk mitigation plan is to perform vibration testing to SPF-MEP vibration levels on an EM PWB with representative components and mass models. Analysis and modeling, along with vibration testing, must prove the PWBA design and demonstrate good rigor to retire the risk Risk rating: Probability 2, Impact 3; not likely to occur based on analysis and modeling and good design practices of the PWBA. Consequences now lowered with addition of ASIC Al cap which lowers structural deflection in areas of concern. Analysis complete, vibe test complete, inspection complete, report released. SPF-DFB02

SPP FIELDS DFB Quarterly Feb 23, 2015 Backup

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Electrical Development Status Completed primary signal integrity measurements; further optimization and verification planned. Signal integrity is good but observed some min and max voltage overshoot and undershoot on memory ICs i/o and control pins. Completing DC Linearity testing of the analog section. Analysis of the results show +/-2 counts error on only the high gain channels. This error is noise due to the gain states and is expected. Completed measurements of EM2 currents/loads on supplies (at room temperature) Sent summary of large current deltas present on assembly to Carl Herman for his magnetic field evaluation Completed and submitted parts stress analysis To Do: Finish frequency response measurements Resolve rework issue with Xilinx DBs Tune Xilinx daughterboard drive strength to determine if overshoots and undershoots can be reduced without series resistor value changes Perform additional board-level testing post-environmental testing Assess data from SCM play-date at SSL Support integrated EM2 with MEP for environmental testing 9

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB Mechanical Development Status Developed a method to dimple the DFB EMI shield to provide dynamic clearance for the capacitors on the S-RAM. Revisited FPGA DB Column Grid Array (CGA) analysis to verify margins. Using the Steinberg closed form equation; the required minimum board frequency is 390Hz, assuming a Ball Grid Array (BGA) in place of the CGA. This assumption is conservative, as the BGA is less compliant than a CGA. For the PWB frequency, depending on the method in which one restrains the board, its’ natural frequency is predicted between 425 to 900Hz. Fields is predicting 925Hz. From the mechanical DFB acceleration test data, the plots indicate a DB natural frequency of ~700Hz. Assuming the interpretation is correct, the test data shows the DB has a 300Hz margin. This margin is quite sufficient with high probability that the CGA FPGA on the DB will survive launch loads. 10 Dimple s DFB EMI Shield

SPP FIELDS DFB Quarterly Feb 23, 2015 DFB FPGA Development Status Lab-level FPGA testing all functionality including: SCM cal, band- pass data, and partial DBM Continued FPGA simulation, lab testing, and bug fixes Continued development of GSEOS test scripts, and test environment Delivered DFB FPGA V.9, includes initial DBM, tested with DCB EM To Do Complete DBM module-level test- bench and associated DBM testing Complete LASP software process documents for SIDECAR firmware Develop automated test scripts for lab testing Rotate SCM 3D signal vectors for spectra by a fixed rotation matrix Continue lab testing, bug fixes, and support testing at SSL Develop self checking test bench Start regression testing late spring 11