Chapter 3 – Instruction Set Architecture

Instruction Length and Cycles

Instruction Length 1 word for instruction Format I: Format II: Format III: OpcodeS-regAdb/wAsD-reg Instruction Length Opcodeb/wAdD/S-reg OpcodeCondition10-bit, 2’s complement PC offset 1 additional word for each of the following addressing modes: Source index mode (As = 01) mov 10(r4),r5 mov cnt,r5 mov &P1IN,r5 Chapter 3 - ISA3 mov #100,r5 Source immediate mode (As = 11, SR = PC) mov r4,10(r5) mov r4,cnt mov r4,&P1OUT Destination index mode (Ad = 1) BYU CS 124

Chapter 3 - ISA4 Quiz 3.5 What is the length (in words) for each of the following instructions? InstructionL L add.w r5,r6mov.w EDE,TONI add.w cnt(r5),r6mov.b @r10+,tab(r6) add.w cnt,r6mov.w #45,TONI add.w &cnt,r6mov.w #2,&MEM add.w #100,r6mov.b #1,r11 mov.w r10,r11mov.w #45,r11 #-1,-1(r15) mov.w Instruction Length BYU CS 124

Chapter 3 - ISA5 Quiz 3.5 (solution) What is the length (in words) for each of the following instructions? InstructionL L add.w r5,r6mov.w EDE,TONI add.w cnt(r5),r6mov.b @r10+,tab(r6) add.w cnt,r6mov.w #45,TONI add.w &cnt,r6mov.w #2,&MEM add.w #100,r6mov.b #1,r11 mov.w r10,r11mov.w #45,r11 #-1,-1(r15) mov.w Instruction Length BYU CS 124

Chapter 3 - ISA6 Finite State Machine Clocks Selects Busses Sensors Registers Phase Memory Registers Phase Multiplexors Decoders WE ALU Drivers Control Logic BYU CS 124 Instruction Clock Cycles Computer Clock

Chapter 3 - ISA7 Processor Speed MCLK – Master Clock Most instruction phases require a clock cycle No clock, no instruction execution CPI – Cycles Per Instruction Average number of clock cycles per complete instruction. MIPS – Millions of Instructions per Second (MIPS) Characterizes a processor’s performance MIPS = MCLK / CPI. Clock speed ≠ faster computer Solution BYU CS 124 Instruction Clock Cycles 4 Steps 8 Steps 2 GHz 1 GHz

Chapter 3 - ISA8 Cycles Per Instruction... Instruction timing: 1 cycle to fetch instruction word +1 cycle if or #Imm +2 cycles if source uses indexed mode 1 st to fetch base address 2 nd to fetch source Includes absolute and symbolic modes +2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory +1 cycle if writing to PC (R0) Jump instructions are always 2 cycles Instruction Clock Cycles BYU CS 124

Chapter 3 - ISA9 Example Cycles/Length... ExampleSrcDstCyclesLength add R5,R8RnRm 1 1 add 2 1 mov 3 1 add R5,4(R6)Rnx(Rm) 4 2 add R8,EDERnEDE 4 2 add R5,&EDERn&EDE 4 2 add #100,TAB(R8)#nx(Rm) 5 3 add &TONI,&EDE&TONI&EDE 6 3 add #1,&EDE#1&EDE 4 2 Instruction Clock Cycles BYU CS 124

Chapter 3 - ISA10 Quiz 3.6 How many cycles for each instruction? ;******************************************************************************* ; CS/ECEn 124 Lab 3 - blinky.asm ;******************************************************************************* ; cycles = --- ; MCLK = --- cycles / 10 seconds = --- Mhz ; CPI = MCLK / --- ; MIPS = MCLK / CPI / = --- MIPS.cdecls C,LIST, "msp430.h" ; MSP430 COUNT.equ 0 ; delay count ; text ; beginning of executable code ; RESET: mov.w #0x0280,SP ; init stack pointer mov.w #0x5a80,&0x0120 ; stop WDT (WDTCTL) bis.b #0x01,&0x0022 ; set P1.0 as output (P1DIR) mainloop: xor.b #0x01,&0x0021 ; toggle P1.0 (P1OUT) mov.w #COUNT,r15 ; use R15 as delay counter delayloop: sub.w #1,r15 ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led ; ; Interrupt Vectors ; sect ".reset" ; MSP430 RESET Vector.word RESET ; start address.end Instruction Clock Cycles BYU CS 124

Chapter 3 - ISA11 Quiz 3.6 (solution) How many cycles for each instruction? ;******************************************************************************* ; CS/ECEn 124 Lab 3 - blinky.asm ;******************************************************************************* ; cycles = --- ; MCLK = --- cycles / 10 seconds = --- Mhz ; CPI = MCLK / --- ; MIPS = MCLK / CPI / = --- MIPS.cdecls C,LIST, "msp430.h" ; MSP430 COUNT.equ 0 ; delay count ; text ; beginning of executable code ; RESET: mov.w #0x0280,SP ; init stack pointer mov.w #0x5a80,&0x0120 ; stop WDT (WDTCTL) bis.b #0x01,&0x0022 ; set P1.0 as output (P1DIR) mainloop: xor.b #0x01,&0x0021 ; toggle P1.0 (P1OUT) mov.w #COUNT,r15 ; use R15 as delay counter delayloop: sub.w #1,r15 ; delay over? jnz delayloop ; n jmp mainloop ; y, toggle led ; ; Interrupt Vectors ; sect ".reset" ; MSP430 RESET Vector.word RESET ; start address.end Instruction Clock Cycles BYU CS 124

Chapter 3 - ISA12 Quiz 3.7 Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay? DELAY.equ ??? mov.w #DELAY,r12 ; delay1: mov.w #1000,r15 ; delay2: sub.w #1,r15 ; jne delay2 ; sub.w #1,r12 ; jne delay1 ; Instruction Clock Cycles BYU CS 124

Chapter 3 - ISA13 Quiz 3.7 (solution) Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay? DELAY.equ ??? mov.w #DELAY,r12 ; 2 cycles delay1: mov.w #1000,r15 ; 2 cycles delay2: sub.w #1,r15 ; 1 cycle jne delay2 ; 2 cycles sub.w #1,r12 ; 1 cycle jne delay1 ; 2 cycles 2 + DELAY  ( ) second = 1,200,000 cycles 0.25 seconds = 1,200,000 / 4 = 300,000 cycles 300,000 cycles = 2 + (DELAY x 3005) cycles – 2 DELAY = = = 100 Instruction Clock Cycles BYU CS 124