Physical Limits of Computing Dr. Mike Frank CIS 6930, Sec. #3753X Spring 2002 Lecture #31 Reversible Processor Architectures Wed., Mar. 27

Administrivia & Overview Don’t forget to keep up with homework!Don’t forget to keep up with homework! –We are  10 out of 14 weeks into the course. You should have earned  ~71 points by now.You should have earned  ~71 points by now. Course outline:Course outline: –Part I&II, Background, Fundamental Limits - done –Part III, Future of Semiconductor Technology - done –Part IV, Potential Future Computing Technologies - done –Part V, Classical Reversible Computing Fri. 3/22: RevComp theory II: Emulating Irreversible Machines RevComp theory II: Bounds on Space-Time OverheadsFri. 3/22: RevComp theory II: Emulating Irreversible Machines RevComp theory II: Bounds on Space-Time Overheads Mon. 3/25: RevComp scaling analysis I: Cost, energy, area-time.Mon. 3/25: RevComp scaling analysis I: Cost, energy, area-time. Wed. 3/27: RevComp scaling analysis II: Spacetime and time.Wed. 3/27: RevComp scaling analysis II: Spacetime and time. Fri. 3/29: Reversible processor architectures.Fri. 3/29: Reversible processor architectures. Mon. 4/1: Reversible programming languages.Mon. 4/1: Reversible programming languages. Wed. 4/3: Reversible algorithms.Wed. 4/3: Reversible algorithms. –Part VI, Quantum Computing - starts Fri. 4/5 –Part VII, Cosmological Limits, Wrap-Up

Why reversible architectures? What about automatic emulation algorithms?What about automatic emulation algorithms? –E.g.: Ben73, Ben89, LMT, Frank02. Transform an irreversible alg. to an equiv. rev’ble one.Transform an irreversible alg. to an equiv. rev’ble one. –But, these do not yield the most cost-efficient reversible algorithms for all problems! E.g., log(R E(i./r) /R on/off ) may be only 0.4 rather than 0.5.E.g., log(R E(i./r) /R on/off ) may be only 0.4 rather than 0.5. Finding the best reversible algorithm requires a creative algorithm discovery process!Finding the best reversible algorithm requires a creative algorithm discovery process! An optimally cost-efficient general-purpose architecture must allow the programmer to specify a custom reversible algorithm that is specific to his problem.An optimally cost-efficient general-purpose architecture must allow the programmer to specify a custom reversible algorithm that is specific to his problem.

Reversibility Affects All Levels As R on/off increases & cost of device manuf. declines (while the cost of energy stays high),As R on/off increases & cost of device manuf. declines (while the cost of energy stays high), –Maximizing overall cost-efficiency requires an increasingly large fraction of all bit-ops be done adiabatically. Maximizing the efficiency of the resulting algorithms, in turn, requires reversibility in:Maximizing the efficiency of the resulting algorithms, in turn, requires reversibility in: –Logic design –Functional units –Instruction set architectures –Programming languages –High-level algorithms Increasing requirement for degree of reversibility Pro- gram- ming model (unless a perfect emulator is found)

All Known Reversible Architectures Ed Barton (MIT class project, 1978)Ed Barton (MIT class project, 1978) –Conservative logic, w. garbage stack Andrew Ressler (MIT bachelor’s thesis, 1979; MIT master’s thesis, 1981)Andrew Ressler (MIT bachelor’s thesis, 1979; MIT master’s thesis, 1981) –Like Barton’s, but more detailed. Paired branches. Henry Baker (1992)Henry Baker (1992) –Reversible pointer automaton machine instructions. J. Storrs “JoSH” Hall (1994)J. Storrs “JoSH” Hall (1994) –Retractile-cascade-based PDP-10-like architecture. Carlin Vieri (MIT master’s thesis, 1995)Carlin Vieri (MIT master’s thesis, 1995) –Early Pendulum ISA, irrev. impl., full VHDL detail. Frank & Rixner (MIT class project, 1996)Frank & Rixner (MIT class project, 1996) –Tick: VLSI schematics & layout of Pendulum subset, w. paired branches Frank & Love (MIT class project, 1996)Frank & Love (MIT class project, 1996) –FlatTop: Adiabatic VLSI impl. of programmable reversible gate array Vieri (MIT Ph.D. thesis, 1999)Vieri (MIT Ph.D. thesis, 1999) –Fully adiabatic VLSI implementation of Pendulum w. paired branches

Reversible Programmable Gate- Array Architectures

(as of May ‘99)

Photo of packaged FlatTop chip

A Bouncing BBMCA “Ball”

A BBMCA Fredkin Gate

Reversible von Neumann Architectures

Reversible Architecture Issues Instruction-Set Architecture (ISA) Issues:Instruction-Set Architecture (ISA) Issues: –How to define irrev. ops (AND, etc.) reversibly? –How to do jumps/branches reversibly? –What kind of memory interface to have? –What about I/O? –How to permit efficient reversible algorithms? –Should the hardware guarantee reversibility? Microarchitectural issues:Microarchitectural issues: –Register file interface –Reversible ALU operations –Shared buses –Program counter control

The Trivial Cases Many typical instructions already reversible:Many typical instructions already reversible: –NOT a Set register a to its bitwise logical complement, a := ~aSet register a to its bitwise logical complement, a := ~a –NEG a Set a to its two’s complement negationSet a to its two’s complement negation a := -a or a := ~a + 1 –INC a Increment a by 1 (modulo 2 ).Increment a by 1 (modulo 2 ). –ADD a b Add register b into register a (a := (a + b) mod 2 )Add register b into register a (a := (a + b) mod 2 ) –XOR a b Exclusive-or b into a (a := a  b)Exclusive-or b into a (a := a  b) –ROL a b Rotate bits in register a left by # positions given by b.Rotate bits in register a left by # positions given by b.

The Nontrivial Cases Other common instructions are not reversible…Other common instructions are not reversible… –CLR a Clear register a to 0.Clear register a to 0. –LD a b Load register a from addr. pointed to by b.Load register a from addr. pointed to by b. –LDI a 3 Load immediate value 3 into register a.Load immediate value 3 into register a. –AND a b Set a to the bitwise AND of a and bSet a to the bitwise AND of a and b –JMP a Jump to the instruction pointed to by a.Jump to the instruction pointed to by a. –SLL a b Shift the bits in a left by b bits, filling with 0’s on right.Shift the bits in a left by b bits, filling with 0’s on right.

Irreversible Data Operations How to do expanding ops reversibly?How to do expanding ops reversibly? –E.g., AND a b - Prior value of a is lost. Approach #1: “Garbage Stack” approach.Approach #1: “Garbage Stack” approach. –Based on Landauer’s embedding. –Push all data that would otherwise be destroyed onto a special “garbage” stack hidden from pgmr. –Can unwind computation when finished to recover stack space. (Lecerf ‘63/Bennett ‘73 approach) Problems: Large garbage stack memory needed.Problems: Large garbage stack memory needed. –Limits computation length. –Leaves programmer no opportunity to choose a more efficient reversible algorithm!

Illustrating Garbage Stack Let “  ” mean reversible move, “  ” mean reversible copy, “  ” a reversible uncopy.Let “  ” mean reversible move, “  ” mean reversible copy, “  ” a reversible uncopy. AND a b implemented by t  a 2. a  t & b 3. t  GSM[GSP++] Garbage Stack Memory (GSM) Garbage Stack Pointer (GSP)

Programmer-Controlled Garbage Put extra data in a programmer-manipulable location.Put extra data in a programmer-manipulable location. –What if destination location isn’t empty? Signal an error, orSignal an error, or Use an op that does something reversible anywayUse an op that does something reversible anyway Provide undo operations to accomplish “unexpanding” inverses of expanding ops.Provide undo operations to accomplish “unexpanding” inverses of expanding ops. 1st method: Errors on non-empty destination:1st method: Errors on non-empty destination: –AND A B C -If (A=0) A  B&C else error –UNAND A B C -If (A=B&C) A  B&C else error 2nd method: Use always-reversible store ops.2nd method: Use always-reversible store ops. –ANDX A B C - A  A  (B & C) (self-undoing!)

Pendulum - packaged chip photo