Distributed Low Voltage Power Supply System for Front End Electronics of the TRT Detector in ATLAS Experiment E.Banaś a, P.Farthouat b, Z.Hajduk a, B.Kisielewski a, P.Lichard b, J.Olszowska a, V.Ryjov b, L.Cardiel Sas b a Henryk Niewodniczański Institute of Nuclear Physics PAN, ul. Radzikowskiego 152, Cracow Poland b CERN, 1211 Geneva 23, Switzerland

27 September 2006LECC Valencia ZH 2 Plan of the talk Introduction System architecture - the components Controls and monitoring Results - examples

27 September 2006LECC Valencia ZH 3 Introduction - TRT detector The TRT (Transition Radiation Tracker) -> the Inner Detector tracking in ATLAS |η|<2.5 in pseudo-rapidity Electron-pion separation at 97% level Continuous tracking with accuracy ~120 μm/point. Barrel and two end-caps arrays of the thin walled proportional counters – straw tubes. Barrel - 96 parts > modules (3 layers of 32) End-caps - 20 ‘wheels’ each, each wheel > 32 sectors. Each module/sector > individual electrical services (HV, LV, timing etc). The detector contains ~ detecting elements - straws.

27 September 2006LECC Valencia ZH 4 TRT detector

27 September 2006LECC Valencia ZH 5 Detector segmentation

27 September 2006LECC Valencia ZH 6 Detector segmentation

27 September 2006LECC Valencia ZH 7 Detector segmentation

27 September 2006LECC Valencia ZH 8 Introduction - FE electronics The front end electronics -> two custom designed ASIC’s: ASDBLR (amplifier-shaper-discriminator-base- line-restorer) DTMROC (drift-time-measuring-read-out-chip) Both chips > radiation hard technologies. Power consumption of channel : ASDBLR ~ 40 mW/channel DTMROC ~ 21 mW/channel

27 September 2006LECC Valencia ZH 9 Introduction - power needs Estimated power dissipation in the front end electronics is ~23 kW. This requires careful design of the cooling system having in mind the confined space where electronics is positioned.

The system - components

27 September 2006LECC Valencia ZH 11 Architecture of the system  Bulk power supplies deliver power to distributors associated with detector geographically defined zones  Voltage distributors supply individual loads splitting the lines received from bulk power supplies

27 September 2006LECC Valencia ZH 12 Bulk power supplies

27 September 2006LECC Valencia ZH 13 Patch Panel board

27 September 2006LECC Valencia ZH 14 Regulators

27 September 2006LECC Valencia ZH 15 Voltage control/setting The regulators used > the adjustable version. Changing the voltage ‘adjust’ input allows output to be set The variable voltage is delivered by radiation hard DAC embedded in the DTMROC chip. The current swing of the DAC output allows for regulators output to be varied by ~0.5V up to 1.2 V. Some F-E parts draw current slightly exceeding the maximum one allowed for the regulators (wheels A). For these channels parallel operation of the regulators has been implemented..

27 September 2006LECC Valencia ZH 16 Voltage control/setting POSITIVE REGULATORS NEGATIVE REGULATORS

27 September 2006LECC Valencia ZH 17 Negative regulation

27 September 2006LECC Valencia ZH 18 Positive regulation

27 September 2006LECC Valencia ZH 19 Current sharing

Controls & monitoring

27 September 2006LECC Valencia ZH 21 MARATON & Framework The MARATON system has been included into FRAMEWORK which makes its integration very easy. Next slide shows typical PVSSII control panel for MARATON system which can be tailored to specific user needs.

27 September 2006LECC Valencia ZH 22 MARATON panel

27 September 2006LECC Valencia ZH 23 DTMROC control ELMB LVDS DTMROC Hard Reset Clock Command In Command Out Digital I/O

27 September 2006LECC Valencia ZH 24 LVPP control circuitry The board contains embedded controller – an ELMB (Embedded Local Monitoring Board). Regulators outputs are connected to the ELMB’s ADC The ADC is measuring the output currents, by monitoring the voltage drop on 22 mOhms serial resistors inserted in output lines Digital ports are used for communications with DTMROC’s

27 September 2006LECC Valencia ZH 25 Controlling DTMROC DTMROC CANBUS Command Out ELMB LVDS DAC0 DAC1 DAC2 DAC3 Hard Reset Clock Command In Digital I/O VR

27 September 2006LECC Valencia ZH 26 Software solutions Implement all algorithms simulating the DTMROC serial protocol in the PVSS layer. The most performant solution would be to modify ELMB firmware embedding in its memory preset bits patterns send to DTMROC by single CAN message. Intermediate solutions would be to use modified software of CANOpen level or one acting directly on the driver by calls to its DLL classes. The attractive, firmware based solution has been dropped. However this remains as possible upgrade for control system in future.

27 September 2006LECC Valencia ZH 27 Control solutions

27 September 2006LECC Valencia ZH 28 DLL Solution adopted -> an extension to the standard PVSS CTRL scripting language which allow for user defined functions to be interpreted by PVSS in the same way as PVSS functions. Initialization of the CANbus, ELMB, DTMROC Operational: Setting DAC’s, Reading back DAC’s, Setting inhibits in DTMROC’s, Reading back inhibit state, Enable/disable and read out OCM state Diagnostics: Reset (soft and hard) of DTMROC’s, Send given number of clocks to DTMROC’s, Get state of a given DTMROC, Set ELMB in the requested state, Read back ELMB state Closing connection

Some examples

27 September 2006LECC Valencia ZH 30 Clock/data generation

27 September 2006LECC Valencia ZH 31 Accesing DTMROC

27 September 2006LECC Valencia ZH 32 Results voltage setting

27 September 2006LECC Valencia ZH 33 Results current measurement

27 September 2006LECC Valencia ZH 34 Results current sharing The plots differ by serial resistor

27 September 2006LECC Valencia ZH 35 Conclusive remarks The tests of complete system have shown that we achieved DTMROC clock frequency ~ 370 Hz. The limiting factor appeared to be the ELMB firmware. This results in ~ 5 sec. for setting one LVPP. The whole TRT can be set in ~ 90 sec’s. If values written in are checked for correctness by read back, quoted time increases to 240 seconds. Since such an operation is foreseen only during cold start up of system (after detector shutdown) this time is deemed fully acceptable. Accuracy of monitoring voltages and current is satisfatory (2-3 % full scale - no calibration)