KU College of Engineering Elec 204: Digital Systems Design 1 Review D: n bit binary number D = (d n-1 ∙ ∙ ∙ d 1 d 0 ) 2 If D is an unsigned binary number D = (2 n-1 d n-1 + ∙ ∙ ∙ 2 1 d d 0 ) 10 If D is a sign-magnitude binary number D = + (2 n-2 d n-2 + ∙ ∙ ∙ 2 1 d d 0 ) 10 if d n-1 =0 = – (2 n-2 d n-2 + ∙ ∙ ∙ 2 1 d d 0 ) 10 if d n-1 =1 (–D) = (d ’ n-1 d n-2 ∙ ∙ ∙ d 1 d 0 ) 2 If D is in two`s complement system D = (-2 n-1 d n n-2 d n-2 + ∙ ∙ ∙ 2 1 d d 0 ) 10 (–D) = 2 n – D = (2 n -1) – D + 1 = (d ’ n-1 d ’ n-2 ∙ ∙ ∙ d ’ 1 d ’ 0 ) 2 + 1

KU College of Engineering Elec 204: Digital Systems Design 2 Two’s complement multiplication –Shift and two’s complement addition except for the last step. Remember MSB represent (-2 n-1 ) x – initial partial product, which is zero partial product partial product shifted-and-negated Review

KU College of Engineering Elec 204: Digital Systems Design 3 BCD: Binary-Coded Decimal 0-9 encoded with their 4-bit unsigned binary representation (0000 – 1001). The codewords (1010 – 1111) are not used. 8-bit byte represent values from 0 to 99. BCD Addition: Carry Sum Add BCD sum BCD result Review

KU College of Engineering Elec 204: Digital Systems Design 4 2. Combinational Logic Circuits Boolean Algebra –switching algebra –deals with Boolean values --- 0, 1 Positive-logic convention –analog voltages LOW, HIGH  0, 1 Negative logic --- seldom used Signal values denoted by variables (X, Y, FRED, etc.)

KU College of Engineering Elec 204: Digital Systems Design 5 Boolean operators Complement:X (opposite of X) AND:X  Y OR:X + Y

KU College of Engineering Elec 204: Digital Systems Design 6 Literal: a variable or its complement –X, X, FRED, CS_L Expression: literals combined by AND, OR, parentheses, complementation –X+Y –P  Q  R –A + B  C –((FRED  Z) + CS_L  A  B  C + Q5)  RESET Equation: Variable = expression –P = ((FRED  Z) + CS_L  A  B  C + Q5)  RESET

KU College of Engineering Elec 204: Digital Systems Design 7 Basic Logic Gates

KU College of Engineering Elec 204: Digital Systems Design 8 Theorems

KU College of Engineering Elec 204: Digital Systems Design 9 More Theorems

KU College of Engineering Elec 204: Digital Systems Design 10 Duality Swap 0 & 1, AND & OR –Result: Theorems still true Why? –Each axiom (T1-T5) has a dual (T1-T5  Counterexample: X + X  Y = X (T9) X  X + Y = X (dual) X + (X  Y) = X (T9) X  (X + Y) = X (dual) (X  X) + (X  Y) = X (T8)

KU College of Engineering Elec 204: Digital Systems Design 11 N-variable Theorems

KU College of Engineering Elec 204: Digital Systems Design 12 DeMorgan Symbol Equivalence

KU College of Engineering Elec 204: Digital Systems Design 13 Similar for OR

KU College of Engineering Elec 204: Digital Systems Design 14 Complement of a function F 1 = XYZ’ + X’Y’Z F 1 ’ = (XYZ’ + X’Y’Z)’ = (XYZ’)’  (X’Y’Z)’ = (X’+Y’+Z)  (X+Y+Z’) Complement = take dual +complement each literal Dual of F 1 = (X+Y+Z’)  (X’+Y’+Z) F 1 ’ = (X’+Y’+Z)  (X+Y+Z’)

KU College of Engineering Elec 204: Digital Systems Design 15 Standard Forms: –Product and sum terms Minterm: A product term in which all variables appear exactly once, either complemented or not (2 n minterms) –For a two variable function, minterms are X’Y’, X’Y, XY’, XY m 0, m 1, m 2, m 3 Maxterms: A sum term that contains all variables in complemented or uncomplemented form X+Y, X+Y’, X’+Y, X’+Y’ M 0, M 1, M 2, M 3

KU College of Engineering Elec 204: Digital Systems Design 16

KU College of Engineering Elec 204: Digital Systems Design 17 Alternative representations –F(X,Y,Z) = X’Y’Z’ + X’YZ’ +XY’Z + XYZ = m 0 + m 2 + m 5 + m 7 = –F’(X,Y,Z) = X’Y’Z + X’YZ + XY’Z’ + XYZ’ = m 1 + m 3 + m 4 + m 6 = –F(X,Y,Z) = (m 1 + m 3 + m 4 + m 6 )’ = m 1 ’ m 3 ’ m 4 ’ m 6 ’ = M 1 M 3 M 4 M 6 =

KU College of Engineering Elec 204: Digital Systems Design 18 Maxterms are seldom used, we’ll use minterms rather. Properties of minterms: –There are 2 n minterms. 1-1 with binary numbers 0-(2 n -1) –Every Boolean function can be expressed as sum of minterms. –Absent minterms belong to complement function –A function that include all minterms is equal to logic 1.