ABC February 2013 ABC 130 Final Design Review 1F. Anghinolfi08/02/13

Introduction What we present today :  A set of responses to the previous review report (see next slides and other talks)  Updated information about the ABC130 front-end (from updated detector parameters after irradiation)  Voltage regulators setup and power up case  Verification processes  Near “final” layout figures  Some open questions, that may impact the submission schedule  Most probable submission scenarios  First evaluations test proposal 2F. Anghinolfi08/02/13

Introduction The ABC130 design team 3F. Anghinolfi08/02/13 PENN Mitch NewcomerSystem, specs, overview Nandor DressnandtIO designs, shunt device Amogh HalgheriInput registers, FastClusterFinder Michal BochenekVoltage Regulator RAL Michelle Key- Charriere Functional Verification Geneva University Daniel La MarraL1-DCL, Top Logic design Santa Cruz Joel de WittCommand decoder, registers, readout and serializer Krakow Krzysztof SwientekEncounter, final DRC and LVS CERN Francis AnghinolfiPipeline and buffers, verifications Jan KaplonFront-End design Piotr RymaszewskiFE layout, power up simulations Filipe SousaTMR insertion C. PaillardSRAM design David MonzatSRAM layout and charact. Bruno AllongueSRAM SEU cross section UCL Samer KilaniR3-DCL

Main Progresses since last review ABC130 :  RTL code completion (but not frozen actually)  ABC ID chip address field moved from 4 to 5 bits (60 bits readout packet)  Adding a 5 bits HCC ID field address to the commands packets (58 bits readout packets instead of 54)  New definition of the command packet to include the HCC commands  (at HCC output) : 64 bits packet size, 2 scrambling options (one is 8b/10b that extends the packet size to 80 bits) 4F. Anghinolfi08/02/13

Main Progresses since last review ABC130 : “What are required operating margins: clock frequencies, cluster search time, trigger rates, data transmission FIFO depth, etc.?” 5F. Anghinolfi08/02/13 Clock FrequenciesSimulation 41.7MHz/166MHz Cluster Search TimeR3 : 4BC (100ns) L1 : 64BC (1.6us) Trigger RatesSimulation 1MHz L0/50KHz R3/200KHz L1 BW limit is reached if packets > 2 per L1 Trigger (6 clusters) FIFO depthsThru aCSR L1 R3 bCSR XOFF stops transfer Required for “all 1”

Main Progresses since last review ABC130 : “Some of the designs show some degree of "committeeization", that is there was a lack of coherence in some cases between design approaches to related problems - for instance in having multiple data compression algorithms or multiple bandgap designs “ BANDGAP : Only one version (3 copies) used in ABC130. Data Compression Algorithm : difference is justified by 1) execution time 2) limited data per event per chip for R3 (one packet only), full data per event per chip for L1 (up to 24 packets) 6F. Anghinolfi08/02/13

Main Progresses since last review ABC130 : “The simulation test bench presented is an excellent tool, and it should be exploited to its fullest extent. An effort should be made by the strip community to document all operation use cases, both for normal operations and exceptions, and these should then be implemented as test bench vectors. All vectors should eventually be run on the final design with timing back-annotation” See status during the presentation on functional verification 7F. Anghinolfi08/02/13

Main Progresses since last review ABC130 : “Models for analog blocks could be produced and included in the test bench simulation. These can be simple models that simply provide dummy values or use register data in dummy ways, or more sophisticated depending on available resourced and usefulness of more sophistication.” Most of the analogue blocks have a functional model where the activity is displayed during functional verification (Regulator ON/OFF, FE block bias change, etc ….) 8F. Anghinolfi08/02/13

Main Progresses since last review ABC130 : “One of the SEU mitigation techniques will be a “watchdog” circuit in the data compression logic to provide a reset if the logic should ever become hung-up. While this technique can resolve such SEU created problems, they can sometime cause their own problems by incorrectly over reacting. The triplication protection of the watchdog circuit should be carefully studied so that its sensitivity is well understood. Francis during the review” The watchdogs are triplicated and used only on the DCL functions. The watchdog can only corrupt the DCL function (ie one packet or serie of packet formation) but not the entire chip. 9F. Anghinolfi08/02/13

ABC130 Physical layout Main Progresses : ABCN:  I/O definition (double size pads), ESD protection devices, and power distribution  Pad ring definition and pads physical layout  Physical layout : Front-End (completed) custom layout Back-end and chip assembly through Encounter (timing constraints are always part of the chip assembly) 10F. Anghinolfi08/02/13

IRRADIATIONS RAM block SEU cross section has been measured at H4IRRAD (Mixed field) from 15 Nov to 3 rd Dec, total fluence 2.5E11HEH/cm2 : cross section 4.8E-14 SEU : ABC 130 in its first version WILL NOT BE “FULLY” protected against SEU errors : a specific/serious program for evaluating the SEU risk should be prepared (resource, money) to run tests with the ABC130 (&HCC) coming versions. 11F. Anghinolfi08/02/13

ABC130 Assembly : The Front_End The Front-End block shows the input (to strip) pads area (on left) then the active area elements (256 channels, center) then in green the power bus bars extending at right to connect to the Analogue power pads across the Digital block On top 2 pads are placed for test purpose FE block size (without power bars extension over the Digital block ) 7862 um x 2615 um 12F. Anghinolfi08/02/13

ABC130 Assembly : Digital Block (BE) Pads ring as agreed with hybrid designers (Ashley, Nobu etc..) Pipeline RAMs Analogue power regulator Shunt Devices (Serial Power) Pipeline RAMs Central part has most of the standard cells logic and will be covered by the analogue power bus extension R3L1 Buffers BE block size 7900 um x 4000 um Digital power regulator R3L1 Buffers 13F. Anghinolfi08/02/13

ABC130 Assembly : Preliminary view Chip size 7900 um x 6700 um 14F. Anghinolfi08/02/13

ABC130 Current Status Actual : – Assembly of FE and BE (Krzysztof (layout)/Francis(functional)) – Encounter : layout verification (DRC, LVS through Calibre and Assura) Next : – Functional verification with delay annotations F. Anghinolfi1508/02/13

Elements discussed by designers FastClusterFinder layout implementation is not done and can be seen as one block delaying the expected submission time Digital power estimates (from tools) are poor : our confidence in numbers is low. eFUSE register implementation adds special constraints : do we need it on this version ? F. Anghinolfi1608/02/13