31nm Al 2 O 3, ZrO 2, HfO 2, … M1 M2 M3 M4 M5 © imec 2002

Logic & Memory 2D interconnect Long lines between logic & memory through bus lines SOC solution: Large die,large size memory cells 3D-SOC interconnect Short, direct lines between Logic & Memory banks

Nanotechnology on smart Si nanoelectronics

Semiconducting nanowires 100nm SiO 2 Ti/TiN: 15nm 30 nm droplet. SiC: 50 nm diel Integrated catalysis

Carbon nanotubes

Wafer thinning 200 mm wafer CMOS wafer, thinned down to 50 µm thickness. Thinning by WSI, France

Scaling Limit of DRAM Maximum electric field Channel length decrease → Channel doping increase → Electric field increase → Junction leakage current increase → Retention time decrease  Cell transistor scaling Gatecontact Electric field distribution ( V/cm )

 Flash + RAM Solution  New Memory Solution Simplified Data Process / No Buffer Memory Simplified Data Process / No Buffer Memory New Memory Applications Mobile Devices

Electroluminescent insulated molecular wires: cyclodextrin-threaded conjugated polyrotaxanes F. Cacialli et al. Nature Materials 1, (2002).

Ultra-high vacuum STM system used for the study

16 octahedral interstices are occupied by Fe 3+ and Fe 2+ ions in equal proportions 8 tetrahedral interstices are occupied by Fe 3+ ions 32 oxygen anions form an f.c.c. lattice Fe 3 O 4 Crystallographic structure