1 Floorplanning of Pipelined Array (FoPA) Modules using Sequence Pairs Matt Moe Herman Schmit

2 Outline Pipelined Arrays Previous Sequence Pair work Sequence Pair additions Results

3 System of the Future Soft IP cores –hardware accelerators –pipelined arrays Microprocessor Control Memory Cryptography Signal Processing

4 Pipelined Arrays Systolic architecture Easy to compile to Fast throughput after synthesis Structure lost during physical design Logic pipeline stage array adjacent pipeline stages

5 Physical Design of Pipelined Arrays Maintain structure One pipeline stage = one floorplan module Use floorplanning tools to create placement constraints Logic array adjacent modules floorplan module

6 How do you maintain the structure? If modules were the same size - trivial solutions

7 More interesting problem… Modules vary in size Wire Congestion –Created by non-adjacency of modules –Forces extra area usage

8 Classic Simulated Annealing of Sequence Pairs Sequence Pair –Floorplan representation that describes directional constraints between every possible pair of blocks –Large design space H. Murata, et.al., “VLSI Module Placement Based on Rectangle Packing by the Sequence Pair,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp , December 1996.

9 Classic Swap Move D A C B A B C D D A C B D A C B A D C B D A C B D A C B D A CB

10 ABCD DACB A B C D D A C B D A C B Oblique Constraint Graph A B C D D A C B D A C B Oblique Connnectivity Graph D A C B

11 FoPA Delete / Insert Move D A C B A B C D D A C B D A C B A B C D D B A C D A C B D A C B

12 D A C B A B C D D A C B D A C B A C B D D A C B D A C B D ACB Restricted Delete / Insert Move

13 This looks better… All logically array adjacent elements are adjacent in the floorplan Reduced wire congestion

14 Floorplanning Results Block sizes created from fastest synthesized designs Each point represents the best score from 10 annealing runs

15 Floorplan Utilization

16 Longest Wire Length

17 Results after Placement and Routing Floorplans used as constraints in Monterey Design System’s Dolphin Iteratively expand floorplans by 1% until routable Delay reported by Dolphin

18 Added Area

19 Added Delay

20 Average Placed and Routed Results Added AreaAdded Delay Unfloorplanned19.95%12.60% Classic41.84%16.96% Classic+LSP37.96%15.51% FoPA15.00%8.50%

21 Conclusions New restricted move set –Creates better placement of modules during floorplanning synthesis –Creates smaller and faster designs after placement and routing In paper –New wire length model –Cost Metric