From Westmere to Magny-cours: Hep-Spec06 Cornell U. - Hepix Fall‘10 INFN - Padova michele.michelotto at pd.infn.it.

Slides:



Advertisements
Similar presentations
 Gain Adjust G1 Gain Adjust G2 Gain Adjust G3 Gain Adjust G4 Phase Adjust P1 Phase Adjust P2 Phase Adjust P3 Phase Adjust P4 t1 t2 t3 t4 Beamformed Sum.
Advertisements

Hepmark project Evaluation of HEP worker nodes Michele Michelotto at pd.infn.it.
OPTERON (Advanced Micro Devices). History of the Opteron AMD's server & workstation processor line 2003: Original Opteron released o 32 & 64 bit processing.
INTEL COREI3 INTEL COREI5 INTEL COREI7 Maryam Zeb Roll#52 GFCW Peshawar.
The i9 Processor From INTEL By: Chad Sheppard. Little info about the new chip Coming from a great line of processors Intel Pentium 1, 2, 3, M, 4, 4HT.
AMD-K7 PROCESSOR Athlon Charles Bovy 24 december 1999.
A comparison of HEP code with SPEC benchmark on multicore worker nodes HEPiX Benchmarking Group Michele Michelotto at pd.infn.it.
Evaluating current processors performance and machines stability R. Esposito 2, P. Mastroserio 2, F. Taurino 2,1, G. Tortone 2 1 INFM, Sez. di Napoli,
HS06 on the last generation of CPU for HEP server farm Michele Michelotto 1.
Moving out of SI2K How INFN is moving out of SI2K as a benchmark for Worker Nodes performance evaluation Michele Michelotto at pd.infn.it.
Processors Menu  INTEL Core™ i Processor INTEL Core™ i Processor  INTEL Core i Processor INTEL Core i Processor  AMD A K.
K10 based AMD processors Dezső Sima Fall 2007 (Ver. 2.1)  Dezső Sima, 2007.
COMPUTER ARCHITECTURE
COMPARISONS 64-bit Intel Xeon X Ghz processors –12 processors sharing 48 GB RAM –Each BARON run restricted to single processor All experiments.
Adam Meyer, Michael Beck, Christopher Koch, and Patrick Gerber.
Different CPUs CLICK THE SPINNING COMPUTER TO MOVE ON.
Intel’s Penryn Sima Dezső Fall 2007 Version nm quad-core -
Processor Development The following slides track three developments in microprocessors since Clock Speed – the speed at which the processor can carry.
High Performance Computing Processors Felix Noble Mirayma V. Rodriguez Agnes Velez Electric and Computer Engineer Department August 25, 2004.
History of Microprocessor MPIntroductionData BusAddress Bus
PDSF at NERSC Site Report HEPiX April 2010 Jay Srinivasan (w/contributions from I. Sakrejda, C. Whitney, and B. Draney) (Presented by Sandy.
HS06 on new CPU, KVM virtual machines and commercial cloud Michele Michelotto 1.
Hyper Threading Technology. Introduction Hyper-threading is a technology developed by Intel Corporation for it’s Xeon processors with a 533 MHz system.
KOLKATA Grid Site Name :- IN-DAE-VECC-02Monalisa Name:- Kolkata-Cream VO :- ALICECity:- KOLKATACountry :- INDIA Shown many data transfers.
News from Alberto et al. Fibers document separated from the rest of the computing resources
Today’s Computers By Sharif Safdary. The right computer for you. Advantages to Laptops Advantages to Laptops Size Size Weight Weight Portability Portability.
CERN IT Department CH-1211 Genève 23 Switzerland t IHEPCCC/HEPiX benchmarking WG Helge Meinhard / CERN-IT LCG Management Board 11 December.
HS06 on last generation of HEP worker nodes Berkeley, Hepix Fall ‘09 INFN - Padova michele.michelotto at pd.infn.it.
Chap 4: Processors Mainly manufactured by Intel and AMD Important features of Processors: Processor Speed (900MHz, 3.2 GHz) Multiprocessing Capabilities.
HS06 performance per watt and transition to SL6 Michele Michelotto – INFN Padova 1.
HEPMARK2 Consiglio di Sezione 9 Luglio 2012 Michele Michelotto - Padova.
I7’s Core. Intel’s Core i7 Content Overview Socket SSE 4.2 Instruction Set Cores –Intel Quickpath Interconnect –Nehalem - new micro-architecture –EP,
Industry Standard Servers Infrastructure Refresh Why?
Programming Multi-Core Processors based Embedded Systems A Hands-On Experience on Cavium Octeon based Platforms Lab Exercises: Lab 1 (Performance measurement)
Computer Performance. Hard Drive - HDD Stores your files, programs, and information. If it gets full, you can’t save any more. Measured in bytes (KB,
Winter 2016CISC101 - Prof. McLeod1 Today How transistors can carry out commands in a CPU. For example, how to add two integers in an integrated circuit.
New CPU, new arch, KVM and commercial cloud Michele Michelotto 1.
The last generation of CPU processor for server farm. New challenges Michele Michelotto 1.
© 2008 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice ProLiant G5 to G6 Processor Positioning.
PASTA 2010 CPU, Disk in 2010 and beyond m. michelotto.
Hardware Architecture
HPC/HTC vs. Cloud Benchmarking An empirical evaluation of the performance and cost implications Kashif Iqbal - PhD ICHEC, NUI Galway,
Moving out of SI2K How INFN is moving out of SI2K as a benchmark for Worker Nodes performance evaluation Michele Michelotto at pd.infn.it.
CERN IT Department CH-1211 Genève 23 Switzerland t IHEPCCC/HEPiX benchmarking WG Helge Meinhard / CERN-IT Grid Deployment Board 09 January.
Sobolev(+Node 6, 7) Showcase +K20m GPU Accelerator.
SI2K and beyond Michele Michelotto – INFN Padova CCR – Frascati 2007, May 30th.
CERN IT Department CH-1211 Genève 23 Switzerland Benchmarking of CPU servers Benchmarking of (CPU) servers Dr. Ulrich Schwickerath, CERN.
Benchmarking of CPU models for HEP application
Morgan Kaufmann Publishers Technology Trends and Performance
Brief introduction about “Grid at LNS”
Itanium® 2 Processor Architecture
Evaluation of HEP worker nodes Michele Michelotto at pd.infn.it
CCR Autunno 2008 Gruppo Server
Hardware 201: Selecting Database Hardware
Gruppo Server CCR michele.michelotto at pd.infn.it
INFN - Padova michele.michelotto at pd.infn.it
Computer Speeds The cost of Computing One Numerical Operation
Worker Node per HEP – Technology update
Solid State Disks Testing with PROOF
How to benchmark an HEP worker node
Lattice QCD Computing Project Review
Low Power processors in HEP
Gruppo Server CCR michele.michelotto at pd.infn.it
How INFN is moving out of SI2K has a benchmark for Worker Nodes
Passive benchmarking of ATLAS Tier-0 CPUs
Evolution of Intel’s Basic Microarchitectures - 2
CERN Benchmarking Cluster
INFN - Padova michele.michelotto at pd.infn.it
CSCE 212 Chapter 4: Assessing and Understanding Performance
Option Pricing Black-Scholes Equation
Presentation transcript:

From Westmere to Magny-cours: Hep-Spec06 Cornell U. - Hepix Fall‘10 INFN - Padova michele.michelotto at pd.infn.it

Processor Available Magny Cours and Westmere now available I’ll show some preliminary result 2michele michelotto - INFN Padova

HEP-SPEC omnetpp 473.astar 483.xalancbmk 444.amd 447.dealII 450.soplex 453.povray Geometric average on 7 tests. Sum on all cores Sum on all Worker nodes michele michelotto - INFN Padova3 Integer tests Floating Point tests

michele michelotto - INFN Padova bit - HT ON/OFF HT ON:81.81 HT OFF: HT OFF is better up to 11concurrent run

michele michelotto - INFN Padova5 5520(2266) vs 2427(2200)

From 2009 to 2010 Intel moved Nehalem to Westmere –From 45 nm to 32 nm –From 4-core/8 logical cpu to 6core/12cpu Amd moved from Instambul to Magny-Cours –From 6 cores to 8/12 cores 6michele michelotto - INFN Padova

Tick Tock m. michelotto 7michele michelotto - INFN Padova

Westmere DP 16 March 2010 first release of Xeon DP on Westmere 32nm m. michelotto modelCores/threadsL3 cacheClock with Turbo Mode Off TDP X5680 6/12 12 MB3.33 GHz130 W X5670 6/12 12 MB2.93 GHz95 W X5660 6/12 12 MB2.80 GHz95 W X5650 6/12 12 MB2.66 GHz95 W L5640 6/12 12 MB2.26 GHz60 W X5677 4/8 12 MB3.46 GHz130 W X5667 4/8 12 MB3.06 GHz95 W E5640 4/8 12 MB2.66 GHz80 W E5630 4/8 12 MB2.53 GHz80 W E5620 4/8 12 MB2.40 GHz80 W L5630 4/8 12 MB2.26 GHz40 W 8michele michelotto - INFN Padova

Westmere 56xx 9michele michelotto - INFN Padova

HT ON vs HT OFF Ottobre CCRmichele michelotto - INFN10

5650 vs 5670pre-rel? Ottobre CCRmichele michelotto - INFN at 2.66 GHz faster than 5670 pre-release at 2.93 GHz? More evident from 10 to 16 instances

AMD Magny-Cours 61xx 12michele michelotto - INFN Padova

Magny-Cours m. michelotto modelCores/threadsL3 cacheClockACP Xeon /12 12 MB2.66 GHz95 W 6124 HE 8/8 12 MB1.8 GHz65 W /8 12 MB1.8 GHz80 W 6128 HE 8/8 12 MB2.0 GHz65 W /8 12 MB2.3 GHz80 W /8 12 MB2.4 GHz80 W 6164 HE 12/12 12 MB1.7 GHz65 W /12 12 MB1.9 GHz80 W /12 12 MB2.1 GHz80 W /12 12 MB2.2 GHz80 W 6176 SE 12/12 12 MB2.3 GHz105 W 13michele michelotto - INFN Padova

5650 vs 6136 Ottobre CCRmichele michelotto - INFN14

5650 vs 6136 Ottobre CCRmichele michelotto - INFN15

6136 (2.3MHz) vs 6128HE (1.8MHZ)

6174 (2.2 GHz) 64 GB 32bit 18michele michelotto - INFN Padova

bit 19michele michelotto - INFN Padova

20 Questions?

Feedback: Privacy Policy Feedback
Do Not Sell My Personal Information
About project: SlidePlayer Terms of Service

© 2025 SlidePlayer.com. Inc. All rights reserved.