1 Pertemuan 9 Mesin ARM: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer ARM ( C4 ) ( No TIK : 4 )

3 Chapter 3. ARM Instruction Set: I

4 LDRR1,NLoadcountintoR1. LDRR2,POINTERLoadaddressNUM1intoR2. MOVR0,#0ClearaccumulatorR0. LOOPLDRR3,[R2],#4LoadnextnumberintoR3. ADDR0,R0,R3AddnumberintoR0. SUBSR1,R1,#1DecrementloopcounterR1. BGTLOOPBranchbackifnotdone. STRR0,SUMStoresum. Figure 3.7. An ARM program for adding numbers.

5 MemoryAddressing addressordata labelOperationinformation AssemblerdirectivesAREACODE ENTRY StatementsthatLDRR1,N generateLDRR2,POINTER machineMOVR0,#0 instructionsLOOPLDRR3,[R2],#4 ADDR0,R0,R3 SUBSR1,R1,#1 BGTLOOP STRR0,SUM AssemblerdirectivesAREADATA SUMDCD0 N 5 POINTERDCDNUM1 DCD3,17,27,12,322 END Figure 3.8. ARM assembly language source program for the program in Figure 3.7.  

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8 LDRR0,POINTERLoadaddressLOCintoR0. LDRBR1,[R0]LoadASCIIcharacters LDRBR2,[R0,#1]intoR1andR2. ANDR2,R2,#&FClearhigh-order28bitsofR2. ORRR2,R2,R1,LSL#4Or[R1]shiftedleftinto[R2]. STRBR2,PACKEDStorepackedBCDdigits intoPACKED. Figure 3.5. An ARM program for packing two 4-bit decimal digits into a byte.

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14 Pertemuan 10 Mesin ARM: II Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

15 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer ARM ( C4 ) ( No TIK : 4 )

16 Chapter 3. ARM Instruction Set: II

17 READLDRR3,[R1]Load[INSTATUS]and TSTR3,#8waitforcharacter. BEQREAD LDRBR3,[R1,#4]Readthecharacterand STRBR3,[R0],#1storeitinmemory. ECHOLDRR4,[R2]Load[OUTSTATUS]and TSTR4,#8waitfordisplay BEQECHOtobeready. STRBR3,[R2,#4]Sendcharactertodisplay. TEQR3,#CRIfnotcarriagereturn, BNEREADreadmorecharacters. Figure 3.9. An ARM program that reads a line of characters and displays it.

18 Callingprogram LDRR1,N LDRR2,POINTER BLLISTADD STRR0,SUM... Subroutine LISTADDSTMFDR13!,{R3,R14}SaveR3andreturnaddressinR14on stack,usingR13asthestackpointer. MOVR0,#0 LOOPLDRR3,[R2],#4 ADDR0,R0,R3 SUBSR1,R1,#1 BGTLOOP LDMFDR13!,{R3,R15 } RestoreR3andloadreturnaddress intoPC(R15). Figure Program of Figure 3.7 written as an ARM subroutine; parameters passed through registers.

19 ADRR1,AVECR1pointstovectorA. ADRR2,BVECR2pointstovectorB. LDRR3,NR3istheloopcounter. MOVR0,#0R0accumulatesthedotproduct. LOOPLDRR4,[R1],#4LoadAcomponent. LDRR5,[R2],#4LoadBcomponent. MLAR0,R4,R5,R0Multiplycomponentsand accumulateintoR0. SUBSR3,R3,#1Decrementthecounter. BNELOOPBranchbackifnotdone. STRR0,DOTPRODStoredotproduct. Figure An ARM dot-product program.

20 Subroutine INSERTIONCMPRHEAD,#0Checkiflistempty. MOVEQRHEAD,RNEWRECIfempty,insertnew MOVEQPC,R14recordashead. LDRR0,[RHEAD]Ifnotempty,checkif LDRR1,[RNEWREC]newrecordbecomes CMPR0,R1newhead,and STRGTRHEAD,[RNEWREC,#4]insertifyes. MOVGTRHEAD,RNEWREC MOVGTPC,R14 MOVRCURRENT,RHEADIfnewrecordgoesafter LOOPLDRRNEXT,[RCURRENT,#4]currenthead, CMPRNEXT,#0findwhere. STREQRNEWREC,[RCURRENT,#4]Newrecordbecomesnewtail. MOVEQPC,R14 LDRR0,[RNEXT]Gofurther? CMPR0,R1 MOVLTRCURRENT,RNEXTYes,thenloopback. BLTLOOP STRRNEXT,[RNEWREC,#4]Otherwise,insertnewrecord STRRNEWREC,[RCURRENT,#4]betweencurrentand MOVPC,R14nextrecords. Figure3.16.AnARMsubroutineforinsertinganewrecordintoalinkedlist.

21 Subroutine DELETIONLDRR0,[RHEAD]Checkifrecordtobe CMPR0,RIDNUMdeletedisthehead. LDREQRHEAD,[RHEAD,#4]Ifyes,delete MOVEQPC,R14andreturn. MOVRCURRENT,RHEADOtherwise,continuesearch. LOOPLDRRNEXT,[RCURRENT,#4]Isnextrecordtheone LDRR0,[RNEXT]tobedeleted? CMPR0,RIDNUM LDREQR0,[RNEXT,#4]Ifyes,delete STREQR0,[RCURRENT,#4]andreturn. MOVEQPC,R14 MOVRCURRENT,RNEXTOtherwise,loopback BLOOPtocontinuesearch. Figure An ARM subroutine for deleting a record from a linked list.

22 TABLE3.1 ARM index addressing modes NameAssemblersyntaxAddressingfunction Withimmediateoffset: Pre-indexed[Rn,#offset]EA=[Rn]+offset Pre-indexed withwriteback[Rn,#offset]!EA=[Rn]+offset; Rn[Rn]+offset Post-indexed[Rn],#offsetEA=[Rn]; Rn[Rn]+offset WithoffsetmagnitudeinRm: Pre-indexed[Rn,Rm,shift]EA=[Rn] m]shifted Pre-indexed withwriteback[Rn,Rm,shift]!EA=[Rn] m]shifted; Rn[Rn] m]shifted Post-indexed[Rn],Rm,shiftEA=[Rn]; Rn[Rn] m]shifted RelativeLocationEA=Location (Pre-indexedwith=[PC]+offset immediateoffset) EA=effectiveaddress offset=asignednumbercontainedintheinstruction shift=direction#integer wheredirectionisLSLforleftshiftorLSRforrightshift,and integerisa5-bitunsignednumberspecifying theshiftamount Rm=theoffsetmagnitudeinregisterRmcanbeaddedtoorsubtractedfromthe contentsofbaseregisterRn            

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25 TABLEB.1 Condition field encoding in ARM instructions Condition NameConditioncode fieldsuffixtest b b EQEqual(zero)Z=1 0001NENotequal(nonzero)Z=0 0010CS/HSCarryset/UnsignedhigherorsameC=1 0011CC/LOCarryclear/UnsignedlowerC=0 0100MIMinus(negative)N=1 0101PLPlus(positiveorzero)N=0 0110VSOverflowV=1 0111VCVCNooverflowV=0 1000HIUnsignedhigherCZ=0 1001LSUnsignedlowerorsameCZ=1 1010GESignedgreaterthanorequalNV=0 1011LTSignedlessthanNV=1 1100GTSignedgreaterthanZ(NV)=0 1101LESignedlessthanorequalZ(NV)=1 1110ALAlways 1111Notused        

26 TABLEB.4 ARM instructions for single word or byte transfer from/to memory MnemonicInstructionOperation (Name)bitsperformed BL LDR01Rd[EA] (Loadword) LDRB11Rd[EA] (Loadbyte) STR00EA[Rd] (Storeword) STRB10EA[Rd] (Storebyte)    