Computer Architecture: Intro Lecture 7- Enhancing performance via pipelining; ASMs as an alternative SM design tool J. Schmalzel S. Mandayam

Simple Model Data Path (7-18) Dbus n-bit bus Signal Dbus Dout Aout FS Status DA AA RW Const MB MD Register File Function Unit MuxB MuxD Din BA

Maximum Clock Rate Consider delays through each functional element—e.g., Register File: 1.4 ns Mux’s: 0.6 ns Function Unit: 2.0 ns F max = 1/T total where T total =  T i For the above example, F max = 1/4.0 = 250 MHz

Considerations for Ti §Combinatorial delays l Propagation delay (numbers of gate levels) l Rise times and fall times §Sequential delays l Propagation delay l Setup and hold times (w.r.t. clock edge)

How to Speed Up Architecture? §Brute force: l Technology speed up (scaling, power) l Parallelism §Architecture alternatives: l Pipelining

Pipeline Registers Insert pipeline register between each significant architectural element Pipeline Register DP Element 3DP Element 2DP Element 1 Speedup is due to sequential clocking through each stage of the pipeline: F max = 1/(T max + T PR ) If we use the same time delays from before, and assume T PR = 0.6 ns, F max = 1/( ) = 385 MHz

4-Stage Pipeline Diagram CK1CK2CK3CK4CK5CK6CK7CK8CK9 1A1B1C1D 2A2B2C2D 3A3B3C3D 4A4B4C4D 5A5B5C5D -- Pipeline fills: CK1-CK3; Pipeline is full: CK4-CK5; Pipeline is emptying: CK6-CK8 Opn # Clock #

Description of Pipeline Diagram §Each stage of the pipeline is denoted as A, B, C, D… §Each operation presented to the pipeline is numbered—e.g., 1, 2, 3… §Each clock is numbered: CK1, CK2… §Flush operation is indicated by “—” which suggests nothing is presented to start of pipeline. In actuality, some other operation sequence would be started, but what is shown emphasizes the fact that it takes 3 additional clock cycles to finish what was started.

Pipeline Issues §Delays due to pipeline filling: No useful output for an N-stage pipeline until N clocks §Highest performance when pipeline is full §Periodic need to flush (empty) the pipeline to accommodate branching, etc.

Algorithmic State Machines (ASMs) §State blocks for Moore (1-hot) machines include a State box and Decision box(es). §State boxes correspond to state bubbles on a SD. §Output list is provided in state box §Outputs of input decision box exit the state block and enter other state boxes. Decision boxes correspond to the input test shown on SD arcs into and out of SD bubbles.

Direct Implementation of 1-hot ASMs §State boxes map to D-F/F’s §State block entries map to OR gates §Decision boxes map to AND gates

Control Path §Hard-wired control §Sequencer §Microprogramming (also may see “Microsequencer”)

Questions, Comments, Discussion