Beam Secondary Shower Acquisition System: Igloo2_UMd_Mezzanine and QIE10 preliminary testing PART II BE-BI-BL Jose Luis Sirvent Blasco 2 Jose Luis Sirvent Blasco PhD. Student STUDENT MEETING 26/01/2015

1. The BWS Readout Upgraded System 1.1 Architecture BE-BI-BL Jose Luis Sirvent Blasco 3 Usage of the GBT link for Data, Control and Timing transmission FE BE GBT 4.8Gbps Beam Synchronous measurements Two serious candidates as readout ASIC for pCVD diamond Detector: ICECAL (LHCb) QIE10 (CMS) We’ll design for tunnel radiation levels: 100Gy/year  up to 1KGy (10 years)

BE-BI-BL Jose Luis Sirvent Blasco 4 1. The BWS Readout Upgraded System 1.2 Front-End Board (QIE10 Acquisiton) Igloo2 UMd Mezzanine Board Experiment CMS: T.Grassi & T. O’Banon Usage: GBT Link for ngCCM QIE10 Mezzanine Board Experiment BI BWS: J.L. Sirvent Usage: Digitalization pCVD Diamond Detector SMA VTRx Power Vcc = 6v SMF 9/125 Control/Debug System seen as a Black Box

BE-BI-BL Jose Luis Sirvent Blasco 5 1. The BWS Readout Upgraded System 1.2 Front-End Board (Assembly tests)

Three TL1963A Regulators: Vin => 6v // Vout => 2,5v, 3.3v & 5v Max Tj => 125 degrees BE-BI-BL Jose Luis Sirvent Blasco 6 1. The BWS Readout Upgraded System 1.3 Front-End Board (Power/Heat dissipation) (1) (2) (3) Where: SupplyIout (mA)Tj_max (deg) 2.5V V V Total Current:1.344 A * The Regulators are hot but within the limits Tjmax < 125deg * Needed to Install a small heat-sink

Three TL1963A Regulators: Vin => 6v // Vout => 2,5v, 3.3v & 5v Max Tj => 125 degrees BE-BI-BL Jose Luis Sirvent Blasco 7 1. The BWS Readout Upgraded System 1.3 Front-End Board (Power/Heat dissipation) (1) (2) (3) Where: SupplyIout (mA)Tj_max (deg) 2.5V V V Total Current:1.344 A * The Regulators are hot but within the limits Tjmax < 125deg * Needed to Install a small heat-sink Remarks: Boards fully powered The link was working perfectly The QIE10 were sending data The In/Out Clocks were correct Currents on the specked values No errors on the link

2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose Luis Sirvent Blasco 8 Link States: 1. Start-up at Test-Mode : Known pattern to check synch. 2. Latency calculation : FE loops data 3. Link on Normal mode 4. Remote QIE10 Initialization 5. Trigger signal for data acquisition 6. Data capture : Stored on BE SDRAM memory 7. Stop Acquisition 8. Post-mortem data transmission SDRAM  PC