The Silicon Pixel Detector (SPD) is part of the Inner Tracking System (ITS) of the ALICE experiment. ALICE is designed to study the properties of strongly interacting matter under the extreme conditions provided by ultrarelativistic nucleus-nucleus collisions at the Large Hadron Collider (LHC) under construction at CERN. The purpose of the SPD is to provide ALICE with adequate secondary vertexing capability for charm and beauty detection in such a high multiplicity environment (charged particle multiplicities of up to 8000 per unit of rapidity have been predicted for head-on Pb-Pb collisions at the LHC). The pseudorapidity coverage of the inner layer is |  | 1.3 GeV/c. THE ALICE SILICON PIXEL DETECTOR SPD Structure The SPD barrel consists of staves distributed in two layers around the beam pipe at a radius of 3.9 cm and 7.6 cm, covering a length of 24.5 cm in z direction. Each stave is formed by 4 ladders, each ladder consisting of a silicon pixel sensor matrix of 256 x 160 cells, bump-bonded to 5 ALICE1LHCb readout chips. The staves are mounted on 10 lightweight carbon-fibre sectors. Thin vessels integrated in the support structure allow the removal by evaporative cooling of the heat generated in the SPD electronics. In total, the ALICE SPD will consist of: staves: 60 ladders: 240 readout chips:1200 pixel cells:≈ 9.8 x 10 6 Bump Bonding The silicon sensors are high resistivity p + n type diodes and are 200  m thick. The readout chip wafers will be thinned (after bump deposition) to ~150  m thickness. Bump- bonding is being prototyped with Pb-Sn solder bumps (VTT, Finland) and Indium bumps (AMS, Italy). Radioactive source measurements with a 55 Fe source conducted in prototype assemblies of 300  m thick sensors bump-bonded to chips of native thickness (750  m) have confirmed the functionality of the devices. SPD Collaboration Dipartimento di Fisica dell’Università e Sezione INFN Bari, Italy Dipartimento di Fisica dell’Università e Sezione INFN Catania, Italy CERN Geneva, Switzerland Slovak Academy of Sciences Kosice, Slovakia Laboratori Nazionali di Legnaro Legnaro, Italy Dipartimento di Fisica dell’Università e Sezione INFN Padova, Italy Dipartimento di Fisica dell’Università ‘La Sapienza’ e Sezione INFN Rome, Italy Dipartimento di Fisica dell’Università e Sezione INFN Salerno, Italy A number of prototype assemblies have been tested in a 350 GeV/c proton beam to measure the resolution, cluster size, and other functional parameters. The July 2002 test setup consisted of 4 singles in two reference planes for tracking, together with a ladder mounted on a positioning table for varying the angle of incidence. The results confirm that the readout chip works to specifications. Test Beam Test beam setup for the latest test beam period (July 2002). Beam profile obtained with the coincidence trigger of 4 scintillating counters to select a 2 x 2 mm 2 beam spot Schematic drawing of the two barrel layers. DAQ The timing, control and readout of each half-stave are done by a PILOT ASIC, mounted on a MCM (Multi Chip Module) together with opto- electronic transceivers and an analog chip providing reference voltages to pixel chips. Clock, trigger and configuration data are sent from the control room via two optical fibers to the PILOT ASIC. Upon reception of a L1 trigger (latency 6  s, rate 1 kHz) data are stored in the multi-event buffers in the pixel chips. Read-out from there is initiated after the reception of a L2 accept signal (latency 100  s, rate 40 to 800 Hz). Data move via the pilot ASIC and the 800 Mb/s G-Link compatible serializer GOL (General Optical Link) on a fiber to the control room. ALICE1LHCb Readout Chip The ALICE1LHCb chip is a mixed-functions ASIC designed in a commercial 0.25  m CMOS process. Radiation hardness is obtained by using enclosed gate NMOS transistors and guard rings. The chip has an active area of 12.8  13.6 mm 2 and comprises 8192 pixel cells, arranged in 256 rows and 32 columns, each cell measuring 50  m (r  )  425  m (z). The nominal frequency of the clock in the experiment is 10 MHz. Chip Tests Test measurements on the ALICE1LHCb chip indicate a minimum operating threshold of about 1000 electrons rms, a mean noise around 110 electrons rms and a threshold spread of about 200 electrons rms before tuning. The pixel wafers containing the ASIC are 200 mm in diameter and each contains 86 chips. Wafer-scale tests have been carried out at CERN on a probe station. The automated test protocol includes current consumption measurements, verification of JTAG and DAC functionality, threshold scan of the complete pixel matrix and determination of minimum threshold. The known-good-die (KGD) yield is higher than 50% (preliminary). VME Master R/O Controlle r Pixel chip Carrier DAQ Adapter Pixel Chip Schematic of the test system. Schematic of the circuitry within one pixel cell. Pixel bus with 10 chips (half-stave configuration). Wafer (200 mm diameter) and KGD map (rejected die in red). ALICE1LHCb chip. Electron microscope photograph of a solder bump on the readout chip. The bump diameter is ~25 microns (courtesy of VTT). Photograph of the carbon fibre support of one sector. router control Tx Digital PILOT Data from the SPD pixel chip 0 pixel chip 9 Analog PILOT data Rx G-link GOL link receiver daughter card Pixel Bus PILOT MCM Counting Room OPS (On detector Pilot System) implementation.