Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis Sajib Kumar Mitra MS/ Department of Computer Science and Engineering University of Dhaka

Overview Background Study  Reversible Logic  Fault Tolerant Method  Online Testability Online Testable Fault Tolerant Circuit Full Adder Circuit  Existing Design  Proposed Design Performance Analysis About Authors Conclusion

Reversible Logic Unique mapping between input and output vectors which governs to have same number of input-output lines of any reversible circuit Recovers heat dissipation unlikely irreversible logic and uses low power CMOS technology Feedback and Fan-out are not allowed Single unit able to compute more than one operation

Reversible Logic (cont…) An (n x n) Reversible Circuit

Reversible Logic (cont…) Unique mapping of Reversible Circuit O1O2O3...OnO1O2O3...On Output Vector I1I2I3...InI1I2I3...In Input Vector

Reversible Logic (cont…) An (n x n) Reversible Circuit Architecture

Reversible Logic (cont…) Reversible EX-OR operation and 2x2 Feynman Gate

Reversible Logic (cont…) Popular 3x3 Reversible Gates

Reversible Logic (cont…) 4x4 Reversible Gates

Reversibility prevents Bit Loss but not able to detect Bit Error or Fault in Circuit

Fault Tolerant Method Bit Error means the alteration of the value of output bits because of internal fault of digital circuit. InputOutput ABAA B What is the meaning of Bit Error? Bit Error in Reversible Circuit

Fault Tolerant Method (cont…) Bit Error means the alteration of the value of output bits because of internal fault of digital circuit. InputOutput ABAA B What is the meaning of Bit Error? Bit Error in Reversible Circuit

Fault Tolerant Method (cont…) Preserves same parity between Input and Output vectors over one to one mapping of reversible circuit Parity Preservation of Reversible Circuit

Fault Tolerant Method (cont…) Let, I v and O v are input and output vectors of a reversible circuit, so the relation is I v ↔O v. But to be a Reversible Fault Tolerant circuit, itself must preserve following equation: where I v ={ I 1, I 2, I 3, …, I n } and O v ={ O 1, O 2, O 3, …, O n } Input Parity = Output Parity

Fault Tolerant Method (cont…) Parity Preservation over reversibility between Input and Output vectors can be realized from the Truth Table of Fredkin Gate as shown below: Fredkin Gate and Corresponding Truth Table InputOutput ABCPQR

Fault Tolerant Method (cont…) InputOutput ABCPQR Fredkin Gate and Corresponding Truth Table Now Verify the following equation:

Fault Tolerant Method (cont…) Fault detection of FRG gate Verify the following equation: Fault exist in Circuit No Fault exist in Circuit

Fault Tolerant Method (cont…) But the minimum dimension of Fault Tolerant gates is 3. Why? Finally Reversible Gate which preserves same parity between input and output vectors is called Fault Tolerant Gate or Parity Preserving Gate InputOutput AA’ x1 Reversible Gate Never be a Fault Tolerant Gate NOT operation

Fault Tolerant Method (cont…) But the minimum dimension of Fault Tolerant gates is 3. Why? InputOutput ABPQ x2 Reversible Gates have no any significance as Fault Tolerant Gate InputOutput ABPQ InputOutput ABPQ InputOutput ABPQ

Fault Tolerant Method (cont…) Existing 3x3 and 4x4 Fault Tolerant Gates

Online Testability Built-In Self Testing method Detects bit-error at outputs of any circuit in run time Reversible gates able to adopt testability feature by deducing output and corresponding input bits To be online testable an ( n x n) reversible gates must preserve the following properties: where I v ={ I 1, I 2, I 3, …, I n } and O v ={ O 1, O 2, O 3, …, O n }

Online Testability (cont…) To be online testable an ( n x n) reversible gates must have the following properties: 3x3 F2G is not online Testable Gates But F2G can be Testable by deducing extra an input and corresponding output line.

Online Testability (cont…) To be online testable an ( n x n) reversible gates must have the following properties: Testing OutputTesting Input

Online Testability (cont…) Verification of Testable F2G at Runtime

Online Testability (cont…) Verification of Testable F2G at Runtime

Online Testability (cont…) Verification of Testable F2G at Runtime

Online Testability (cont…)

Operational Outputs Testing Outputs Testing Inputs (Constant Value) Operational Inputs TRC is a Cascading Block not Gate

Online Testability (cont…) Conversion of nxn Reversible Gate into (n+2)x(n+2) reversible Cell Testable R based on following Law: Testable Reversible Cell by using Cascading Attachment

Reversible Fault Tolerant Full Adder Circuit Full Adder circuit produces Sum and C out as following equations respectively: Full Adder can be realized by using only one MTSG gate as follows:

Reversible Fault Tolerant Full Adder Circuit (cont…) Pros o Garbage = 2 o Gate = 1 o Quantum Cost = 6 Cons Neither Fault Tolerant nor Online testable You have to make Fault Tolerant and Online Testable circuit by using fault Tolerant Gates. So start now…

Existing Fault Tolerant Fault Tolerant Adder Circuit By using MIG… Design is Fault tolerant but uses higher dimensional reversible Gates To make online testable, circuit has to increase an extra input-output line

Proposed Design of Fault Tolerant Full Adder Uses 3x3 Fault Tolerant gates Easily adoptable to online testable full adder Minimum number of Garbage, 3 Preferable for Carry Look Ahead adder

Proposed Design of Online Testable Fault Tolerant Full Adder

Performance Analysis Fault Tolerant Full Adder Total Gates Total Garbage Quantum Cost 3x34x4 Proposed [b]40311 Existing [a]02314 Table 1: Comparison between proposed and existing design

About Author Ahsan Raja Chowdhury received his B.Sc.and MS degrees in Computer science and Engineering from the University of Dhaka, Bangladesh, in 2004 and 2006, respectively. He worked with the Department of Computer Science and Engineering, Northern University, Bangladesh, from 2004 to 2007 as faculty member. He is the faculty member of the Department of Computer Science and Engineering, Sajib Kumar Mitra is an MS student of Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interests include Electronics, Digital Circuit Design, Logic Design, and Reversible Logic Synthesis. Md. Faisal Hossain has completed his undergraduate from Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interest includes Logic Design, especially Reversible Logic Design.

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