ASIC 120: Digital Systems and Standard-Cell ASIC Design Design Challenge 1: Jeff’s Solution November 2, 2005

Disclaimer These solutions may not be correct In fact, they haven’t even been tested –tested solutions to come later

Question 1 (a) Many cryptographic systems rely on modular arithmetic. An example would be “clock arithmetic”, where when you add 7 hours to 9 o’clock, it becomes 4 o’clock, not 16 o’clock. In this case the modulus would be 12. Design an 4-bit adder that adds modulo 16. That is, given inputs a and b, find a + b (mod 16).

Question 1 (a) two number adder: process begin wait until rising_edge(clk); c <= a + b; end process;

Question 1 (a) two number adder with mod 4: process begin wait until rising_edge(clk); c <= (a + b) mod 4; end process;

Question 1 (a) This is not easily synthesizable –good for high level design (behavioural design) –how is addition handled? –what does mod 4 really mean? How is it handled?

Question 1 (a) two number adder with extra stuff: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; … signal a, b, c : std_logic_vector(3 downto 0); signal tmpc : unsigned(3 downto 0); … process begin wait until rising_edge(clk); tmpc <= unsigned(a) + unsigned(b); c <= std_logic_vector(tmpc); end process;

Question 1 (a) two number adder with selected extra stuff, mod 4: … signal a, b, c : std_logic_vector(3 downto 0); signal tmpa, tmpb, tmpc : unsigned(4 downto 0); … process begin wait until rising_edge(clk); tmpa <= ‘0’ & unsigned(a); tmpb <= ‘0’ & unsigned(b); tmpc <= tmpa + tmpb; c <= ‘0’ & std_logic_vector(tmpc(3 downto 0))(2 downto 0); end process;

Question 1 (a) Where was the “mod 4” –since 4 is a power of two, we could just “chop off” the higher order bits, which we did with the line c <= ‘0’ & std_logic_vector(tmpc(3 downto 0))(2 downto 0); Always look for powers of 2 when –multiplying –dividing –modding

Question 1 (b) Many cryptographic systems rely on modular arithmetic. An example would be “clock arithmetic”, where when you add 7 hours to 9 o’clock, it becomes 4 o’clock, not 16 o’clock. In this case the modulus would be 12. Design a 4-bit adder that adds modulo 23. Public key applications such as Diffie-Hellman key exchange use prime numbers for their modulus for their properties.

Question 1 (b) We can’t use the same trick as last time –23 is not a power of 2 How do we multiply, divide, or add by a power that is not 2?

Question 1 (b) One way: use repeated addition or subtraction Consider the following setup: process begin wait until rising_edge(clk); in_num_a <= ‘0’ & unsigned(in_val_a); in_num_b <= ‘0’ & unsigned(in_val_a); tmp_num_c <= in_num_a + in_num_b; [ mod stuff here ] end process;

Question 1 (b) Using the previous setup: … while (tmp_num_c > 22) loop wait until rising_edge(clk); tmp_num_c <= tmp_num_c – 23; end loop; out_val_c <= std_logic_vector(tmp_num_c(3 downto 0)); …

Question 1 (b) What would the signal declarations look like? Possibly: signalin_val_a, in_val_b, out_val_c : std_logic_vector(3 downto 0); signalin_num_a, in_num_b, tmp_num_c : unsigned(4 downto 0);

Question 1 (b) Possible enhancement: –add control signals process begin while (start_mod = ‘0’) loop done_mod <= ‘0’; wait until rising_edge(clk); end loop; [ do add and mod ] done_mod <= ‘1’; wait until rising_edge(clk); end process;

Question 2 Linear Feedback Shift Registers (LFSRs) are used in many cryptographic applications. At its core an LFSR is just a series of D Flip Flops, and a feedback that combines certain elements with XORs. (See diagram below.) All the Ds in this diagram are LFSRs, and the bottom is an XOR. Implement this LFSR.

Question 2 Let’s break the question down First, consider four chained D Flip Flops (DFFs) labelled A, B, C, D: signal a, b, c, d : std_logic; … process begin wait until rising_edge(clk); a <= ff_input; b <= a; c <= b; d <= c; end process;

Question 2 Consider four chained (DFFs) with feedback from D to A: process begin wait until rising_edge(clk); a <= d; b <= a; c <= b; d <= c; end process;

Question 2 Consider four chained (DFFs) with feedback from D to A with an XOR gate: process begin wait until rising_edge(clk); a <= a xor d; b <= a; c <= b; d <= c; end process;

Question 2 But what are the initial values? –we could preload some process begin a <= ‘0’; b <= ‘0’; c <= ‘0’; d <= ‘0’; loop wait until rising_edge(clk); a <= a xor d; b <= a; c <= b; d <= c; end loop; end process;

Question 2 Or we could set some at will –note the included reset option process begin wait until rising_edge(clk); if (reset = ‘1’) then a <= ‘0’; b <= ‘0’; c <= ‘0’; d <= ‘0’; elsif (load = ‘1’) then a <= ld_a; b <= ld_b; c <= ld_c; d <= ld_d; else a <= a xor d; b <= a; c <= b; d <= c; end if; end process;

UW ASIC Design Team reference material –Accolade VHDL reference (excellent!): many of today’s examples came from here –Bryce Leung’s tutorials (UW ASIC website) –Mike Goldsmith’s tutorials (UW ASIC website) –your course notes my contact info: Jeff Wentworth,