GTP Update 3 March Cuevas

CPUPP17PP15PP13PP11PP09PP07PP05PP03PP01SWASWBPP02PP04PP06PP08PP10PP12PP14PP16PP18 64x***SSP GTPA GTPB SSP TI DP1LVPECL Trig1 In DP2LVPECL Sync In DP3LVPECL CLOCK In DP4LVPECL Trig2 In DP5SSP_ALANE_Tx0 DP6SSP_ALANE_Tx1 DP7SSP_ALANE_Tx2 DP8SSP_ALANE_Tx3 SE1BUSY SE2LINKUP DP23LVPECL Trig1 In DP24LVPECL Sync In DP25LVPECL CLOCK In DP26LVPECL Trig2 In DP27SSP_BLANE_Tx0 DP28SSP_BLANE_Tx1 DP29SSP_BLANE_Tx2 DP30SSP_BLANE_Tx3 SE7BUSY SE8LINKUP DP1CLOCK_A DP2CLOCK_B DP3Not Used DP4SYNC DP5TRIG1 DP6TRIG2 DP7CTP/GTP_LINK DP8BUSY SE1SCL_SWA SE2SDA_SWA DP23CLOCK_A DP24CLOCK_B DP25Token_Out DP26SYNC DP27TRIG1 DP28TRIG2 DP29SD/GTP_LINK DP30BUSY SE7SCL_SWB SE8SDA_SWB GTP (A) GTP (B) DP1LVPECL Trig1 In DP2LVPECL Sync In DP3LVPECL CLOCK In DP4LVPECL Trig2 In DP5SSP_ALANE_Tx0 DP6SSP_ALANE_Tx1 DP7SSP_ALANE_Tx2 DP8SSP_ALANE_Tx3 SE1BUSY SE2LINKUP DP23LVPECL Trig1 In DP24LVPECL Sync In DP25LVPECL CLOCK In DP26LVPECL Trig2 In DP27SSP_BLANE_Tx0 DP28SSP_BLANE_Tx1 DP29SSP_BLANE_Tx2 DP30SSP_BLANE_Tx3 SE7BUSY SE8LINKUP TI PP18 PP-01 PP-08 4 Pair ‘Simplex’ PP17 (CPU) 1 ‘Lane’ *** If CPU is a VXS payload, it will occupy PP17 Plan to implement 1 lane to both GTPA and GTPB PP01 - PP08 Sub-System Processor Pair Mapping ( Eight SSP shown in crate map table below) ( 64 Front-End Crates ) 21 Slot VXS Crate Map Payload Ports 4 Pair ‘Simplex’ 4 Pair ‘Simplex’ 4 Pair ‘Simplex’ 1 ‘Lane’ Global Trigger Crate Logical Pair Map 2

Original Specification April 2008 in preparation for CD3 Review Ben Raydo  6 FPGA  Significant routing between chips  Virtex 5 Experience with CTP  Expensive (But only two per Hall)  Preliminary firmware tested and meets timing latency requirements 3Cuevas

64xPP17PP15PP13PP11PP09PP07PP05PP03PP01SWASWBPP02PP04PP06PP08PP10PP12PP14PP16PP18 CPU SSP GTPA GTPB SSP TI DP5SSP_ALANE_Tx0 DP6SSP_ALANE_Tx1 DP7SSP_ALANE_Tx2 DP8SSP_ALANE_Tx3 SE2LINKUP SE1SCL_SWA SE2SDA_SWA DP1CLOCK_A DP2CLOCK_B DP3Not Used DP4SYNC DP5TRIG1 DP6TRIG2 DP7CTP/GTP_LINK DP8BUSY GLOBAL TRIGGER PROCESSOR TI PP18 SSP-1 PP17 (CPU) 1 ‘Lane’ Ethernet CPU is a GE_FANUC with VXS connection (PP-17) To each GTP (Switch Slot) Linux OS PP1 - PP16 Sub-System Processor Pair Mapping ( Eight SSP shown in crate map table below) ( 64 Front-End Crates ) 21 Slot VXS Crate Map 2.5Gbps X 4 ‘Simplex’ SSP-8 DP1LVPECL Trig1 In DP2LVPECL Sync In DP3LVPECL CLOCK In DP4LVPECL Trig2 In SE1BUSY Tx Rx DP5SSP_ALANE_Tx0 DP6SSP_ALANE_Tx1 DP7SSP_ALANE_Tx2 DP8SSP_ALANE_Tx3 SE2LINKUP SSP-8 DP1LVPECL Trig1 In DP2LVPECL Sync In DP3LVPECL CLOCK In DP4LVPECL Trig2 In SE1BUSY SSP-1 XC5VTX150T-1156 FPGA Fabric Contains Forty (40) Gigabit Transceivers 8 Trigger Bits To TS 2.5Gbps X 4 ‘Simplex’ Front Panel I/O 4 In/4 Out ** Front Panel JTAG Power Section +5V DC Configuration EEPROM Return I^2C 250MHz SYNC TRIG1 TRIG2 Global Trigger Logic Equations All Logic consolidated In 1 Device 250MHz SYNC TRIG1 TRIG2 Signal Distribution Section 4

 Very quick component layout using 1 FPGA idea  Routing will be dense for the Gigabit links from Each SSP ( 4 links X 8 SSP )  GTP must manage the SD functions, but this should be feasible. Power and cost are reduced from original proposal Need to re-synthesize Ben’s code in new part START Schematic! 5Cuevas