Architecture optimization and design verification of the Timepix3 and the Velopix pixel ASICs Tuomas Poikela (TUCS/CERN) SV/UVM Mini workshop

Outline  Introduction (Pixel chip & TLM)  Architecture optimization  Transaction level model (TLM)  Integration with verification environment  Design verification  Reusing modeling framework  Testbench architecture  Assertions SV/UVM workshop T. Poikela2

Introduction  Techniques presented here used in two pixel ASIC projects: Timepix3 and Velopix  256x256 pixel ASICs with 55um x 55um pitch, designed using 130nm CMOS  Timepix3 has been manufactured and tested to work (characterization not fully done yet)  Velopix is still a work in progress, but the design is very well advanced SV/UVM workshop T. Poikela3

Pixel readout chip interfaces Slow control Input interface (sensor/ discriminators) Pixel matrix (active area) Data outputs TFC (reset, sync, etc.) Periphery SV/UVM workshop T. Poikela4

TLM notation Get-interface Put-interface Bit-level interface Analysis- interface Components (agents, scoreboards, BFMs…) Initiator port Target port/export SV/UVM workshop T. Poikela5

ARCHITECTURE OPTIMIZATION SV/UVM workshop T. Poikela6

Testbench for optimization Input agent Input agent Pixel ASIC TLM DUT ( ovm_component ) Pixel ASIC TLM DUT ( ovm_component ) Output agent TLM Scoreboard Test class ( ovm_test ) Sequence library Configuration object SV/UVM workshop T. Poikela7 Discriminator interface Output data interface

Pixel ASIC TLM Pixel ASIC TLM DUT ( ovm_component ) Virtual router Virtual router Column 0 Column 1 Column 1 Column N Periphery Bus Arbiter Not all TLM ports/components shown inside the periphery. FIFO Output block Each port specialized for packet transaction SV/UVM workshop T. Poikela8 All components modelled as ovm_component s. All components modelled as ovm_component s.

Transaction definition Each TLM port in TLM model specialized with TPX2PacketTransaction SV/UVM workshop T. Poikela9

TLM Framework SV/UVM workshop T. Poikela10 Sequence & test libraryComponent library Arbiter base Arbiter base Token Arbiter Token Arbiter Column Base Column Base SuperPixel Column Pixel Column Pixel Column PeripheryBase EoCBase EoC Arbitrated EoC Arbitrated ColumnBus PeripheryBus ChipBase Chip0 Chip1 extends BaseSeq class TestBase; ChipBase chip; BaseSeq seq; Random Seq Monte CarloSeq Class Test0 extends TestBase; Class Test1 extends TestBase; set_type_override( ChipBase, Chip0) set_type_override( ChipBase, Chip1) set_type_override( BaseSeq, RandomSeq)

Different modeling approach (non- TLM/OVM) SV/UVM workshop T. Poikela11 class TopLevelSim; Pixel Matrix Periphery module TopLevel_tb; Packet creator Monte Carlo data Constrained Random Data generator Constrained Random Data generator (Ideally one object at top-level) Packet Pool Packet Pool Scoreboard Result extraction TopLevelSim simulation = new; initial simulation.run(); Chip model List of packets

Simulation main loop SV/UVM workshop T. Poikela12 Completely untimed style  Can use C++ as well  Seems to be 4-8 x faster than TLM model Can add timing by using #25ns; No performance loss.

DESIGN VERIFICATION SV/UVM workshop T. Poikela13

RTL Verification Environment Input agent Input agent Pixel Trans- actor Output agent Slow Control Agent Slow Control Agent TFC Agemt TFC Agemt RTL Scoreboard (hierarchical) Configura tion registers Register updater Register updater Output Trans- actor Pixel ASIC RTL DUT Pixel ASIC RTL DUT Conver ter Test class ( ovm_test ) Configuration Virtual Sequencer Virtual Sequencer SV/UVM workshop T. Poikela14

Test base class SV/UVM workshop T. Poikela15 Test base class Actual, derived test

Scoreboard block diagram RTL Scoreboard (hierarchical) Datapath scoreboard Packet generator Write Implem. Write Implem. Control packet scoreboard Slow control Scoreboard Slow control Scoreboard Configura tion registers SV/UVM workshop T. Poikela16 Black box view White box view ErrorDB PacketDB Checker

Configuration registers  Created in test class  Passed to components inside a config object  Each register is an ovm_object, has a coverage model  Only handful of registers but > 800 LOCs of SV (excluding drivers, macros etc.) SV/UVM workshop T. Poikela17 Configuration registers, ovm_object Pixels PLL General Output block Output block Test pulse Power pulsing Power pulsing Analog config Analog config Register package + register typedefs Typedef struct {… …} PixelReg_t; + register typedefs Typedef struct {… …} PixelReg_t;

Assertions – using macros Source: C. E. Cummings. SystemVerilog Assertions Design Tricks and SVA Bind Files SV/UVM workshop T. Poikela18

Assertions cont’d SV/UVM workshop T. Poikela19 No error. Data stable 1 clock before and after. No error. Data stable 1 clock before and after. ERROR. Data changed 1 clock before req. ERROR. Data changed 1 clock before req. ERROR. Data changed 1 clock after req. ERROR. Data changed 1 clock after req.

Scripting flow Test library + verif. environment Test library + verif. environment Top-level modules Top-level modules IUS simulation scripts -one per module IUS simulation scripts -one per module IUS compilation scripts IUS compilation scripts System Verilog code Simulator Shell PERL script Test list 0 Test list N regress.pl work_dir0 work_dir1 work_dirN./regress.pl -f ius_script.f -t test_list_N.t Sequence library Coverage Master log file Run 0 log file Run N log file Simulations logs Results SV/UVM workshop T. Poikela20

Concluding remarks  Few use cases of SV + OVM have been presented  Modeling of a pixel chip  RTL verification: Testbench structure using OVM  Plan is to move to UVM for Velopix (and maybe change the high-level model from TLM/OVM to pure SV)  Use assertions! SV/UVM workshop T. Poikela21

THANK YOU FOR THE ATTENTION! SV/UVM workshop T. Poikela22