Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: October 3, 2011 Variation

Previously Understand how to model transistor behavior Given that we know its parameters –V dd, V th, t OX, C OX, W, L, N A … Penn ESE370 Fall DeHon 2 C GC C GCS C GCB

But… We don’t know its parameters (perfectly) 1.Fabrication parameters have error range 2.Identically drawn devices differ 3.Parameters change with environment (e.g. Temperature) 4.Parameters change with time (aging) Why I am more concerned with robustness than precision. Penn ESE370 Fall DeHon 3

Today Sources of Variation –Fabrication –Operation –Aging Coping with Variation –Margin –Corners –Binning Penn ESE370 Fall DeHon 4

Fabrication Penn ESE370 Fall DeHon 5

Process Shift Oxide thickness Doping level Layer alignment Growth and Etch rates and times –Depend on chemical concentrations How precisely can we control those? Vary machine-to-machine, day-to-day Impact all transistors on wafer Penn ESE370 Fall DeHon 6

Systematic Spatial Parameters change consistently across wafer or chip based on location Chemical-Mechanical Polishing (CMP) –Dishing Lens distortion Penn ESE370 Fall DeHon 7

FPGA Systematic Variation 65nm Virtex 5 Penn ESE370 Fall DeHon 8 [Tuan et al. / ISQED 2010]

Penn ESE370 Fall DeHon 9 Oxide Thickness [Asenov et al. TRED 2002]

Penn ESE370 Fall DeHon 10 Line Edge Roughness 1.2  m and 2.4  m lines From:

Optical Sources What is the shortest wavelength of visible light? How compare to 45nm feature size? Penn ESE370 Fall DeHon 11

Penn ESE370 Fall DeHon 12 Phase Shift Masking Source Today’s chips use λ =193nm

Penn ESE370 Fall DeHon 13 Line Edges (PSM) Source:

Penn ESE370 Fall DeHon 14 Intel 65nm SRAM (PSM) Source:

Penn ESE370 Fall DeHon 15 Statistical Dopant Placement [Bernstein et al, IBM JRD 2006]

Random Trans-to-Trans Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates –Stochastic process Transistors differ from each other in random ways Penn ESE370 Fall DeHon 16

Penn ESE370 Fall DeHon 17 Source: Noel Menezes, Intel ISPD2007

Impact Changes parameters –W, L, t OX, V th Change transistor behavior –W? –L? –t OX? Penn ESE370 Fall DeHon 18

Example: V th Many physical effects impact V th –Doping, dimensions, roughness Behavior highly dependent on V th Penn ESE370 Fall DeHon 19

Penn ESE370 Fall DeHon 20 V th 65nm [Bernstein et al, IBM JRD 2006]

Penn ESE534 Spring DeHon 21 Impact of V th Variation? Higher V TH ? –Not drive as strongly –I d,sat  (V gs -V TH ) 2 –Performance?

Impact Performance V th  I ds  Delay (R on * C load ) Penn ESE370 Fall DeHon 22

Impact of V th Variation Penn ESE370 Fall DeHon 23 Think NMOS Vgs = Vdd

FPGA Logic Variation Xilinx Virtex 5 65nm Penn ESE370 Fall DeHon 24 [Wong, FPT2007] Altera Cyclone-II 90nm [Tuan et al. / ISQED 2010]

Penn ESE534 Spring DeHon 25 Impact of V th Variation? Lower V TH ? –Not turn off as well  leaks more

Penn ESE370 Fall DeHon 26 Borkar (Intel) Micro 37 (2004) 2004

Operation Temperature Voltage Penn ESE370 Fall DeHon 27

Temperature Changes Different ambient environments –January in Maine –July in Philly –Air conditioned machine room Self heat from activity of chip Quality of heat sink (attachment thereof) Penn ESE370 Fall DeHon 28

Self Heating Penn ESE370 Fall DeHon 29 Borkar (Intel) Micro 37 (2004)

Temperature (on current?) High temperature –More free thermal energy Easier to conduct Lowers V th –Increase rate of collision Lower saturation velocity Lower saturation voltage Lower peak I ds  slows down Another reason don’t want chips to run hot Penn ESE370 Fall DeHon 30

Temperature (leakage?) High temperature Lowers V th Penn ESE370 Fall DeHon 31

Voltage Power supply isn’t perfect Differs from design to design –Board to board? –How precise is regulator? IR-drop in distribution Bounce with current spikes Penn ESE370 Fall DeHon 32

Aging Hot Carrier NBTI Penn ESE370 Fall DeHon 33

Hot Carriers Trap electrons in oxide –Also shifts V th Penn ESE370 Fall DeHon 34

NBTI Negative Bias Temperature Instability –Interface traps, Holes Long-term negative gate-source voltage –Affects PFET most Increase V th Partially recoverable? Temperature dependent Penn ESE370 Fall DeHon 35 [Stott, FPGA2010]

Measured Accelerated Aging (Cyclone III, 65nm FPGA) Penn ESE370 Fall DeHon 36 [Stott, FPGA2010]

Coping with Variation Penn ESE370 Fall DeHon 37

Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Penn ESE370 Fall DeHon 38

Penn ESE534 Spring DeHon 39 Impact of Vth Variation Higher V TH –Not drive as strongly –I d,sat  (V gs -V TH ) 2 Lower V TH –Not turn off as well  leaks more

Penn ESE370 Fall DeHon 40 Variation Margin for expected variation Must assume V th can be any value in range –Speed  assume V th slowest value Probability Distribution V TH I on,min =I on (V th,max ) I d,sat  (V gs -V th ) 2

Gaussian Distribution Penn ESE534 Spring DeHon 41 From:

Impact Given –V th,nom = 250mV –Sigma 25mV What maximum V th should expect to see for a circuit of –100 transistors? –1000 transistors? –10 9 transistors? Penn ESE370 Fall DeHon 42

Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Validate design at extremes –Work for both V th,min and V th,max ? –Design for worst-case scenario Penn ESE370 Fall DeHon 43

Margining Also margin for –Temperature –Voltage –Aging: end-of-life Penn ESE370 Fall DeHon 44

Process Corners Many effects independent Many parameters With N parameters, –Look only at extreme ends (low, high) –How many cases? Try to identify the {worst,best} set of parameters –Slow corner of design space, fast corner Use corners to bracket behavior Penn ESE370 Fall DeHon 45

Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Penn ESE370 Fall DeHon 46 Probability Distribution Delay

Penn ESE370 Fall DeHon 47 Speed Binning Probability Distribution Delay Discard Sell Premium Sell nominal Sell cheap

Admin HW4 out –All but question 5 should be approachable now Andre out Tuesday Andre back for lecture on Wednesday –Talk about layout … HW4.Q5 First midterm W after break Penn ESE370 Fall DeHon 48

Idea Parameters Approximate Differ –Chip-to-chip, transistor-to-transistor, over time Robust design accommodates –Tolerance and Margins –Doesn’t depend on precise behavior Penn ESE370 Fall DeHon 49