Robust Low Power VLSI R obust L ow P ower VLSI My Research Topics Alicia Klinefelter Dept. of Electrical Engineering, University of Virginia January 23, 2012

Robust Low Power VLSI Areas  Cyber-physical Systems (CPS)  Deliverable: Hardware for CPS system  NEMO  Deliverable: Whale tag  All-Digital Phase-Locked Loop (ADPLL)  Have taped out  Testing is next  Simulink Model For Ultra- Low Power Systems 2 [1] [2] [1] [2]

Robust Low Power VLSI Context/Problems  CPS  Context: Want to combine the cyber (computational) and physical (body) aspects of body sensor nodes to create a network.  Problem: Incorporating multiple disciplines in one project and choosing the right architecture.  NEMO  Context: Debate exists on whether whales are affected by sonar from submarines. Record the sounds the whale hears and the depth and length of its dives.  Problem: Low-power chip that can interface with non-volatile memory and interface to a variety of sensors. Determine divide between analog and digital processing.  ADPLL  Context: Result of a class project on PLL’s  Problem: Most ADPLLs consume mW of power and still contain analog components. 3

Robust Low Power VLSI Approach/Findings  CPS  Approach: Work on modeling system architecture. In the meantime, develop plan for hardware.  Findings: Comprehensive model is difficult to pin down.  NEMO  Approach: Model small sections of the system (NVM interface, interfacing to sensors)  Hope to find: Analog/Digital partition, low-power signal processing.  ADPLL  Approach: Replace analog elements with digital elements and operate in sub-threshold for a coarse clock.  Findings: Sub-threshold limits max operating frequency of ring- oscillator, accuracy of time-to-digital converter, and time to lock. 4

Robust Low Power VLSI Questions? 5