Onchip Interconnect Exploration for Multicore Processors Utilizing FPGAs Graham Schelle and Dirk Grunwald University of Colorado at Boulder

Outline Network on Chip (NoC) defined Network on Chip (NoC) defined Current onchip interconnect tools Current onchip interconnect tools NoCem (NoC Emulator) specification NoCem (NoC Emulator) specification What else is needed before release What else is needed before release We want it to be used…and cited We want it to be used…and cited Conclusions Conclusions

Network on Chip Defined (in 1 slide!) Power/design concerns in modern processors lead to multicore chips Transistors seen as “free” allowing more transistors for non- computational tasks Network on Chip Networking scales to infinite number of access points and is well understood High speed clocking leads to signals not propagating across chip in single cycle

Onchip Interconnects for FPGAs Existing Buses on FPGAs Existing Buses on FPGAs PLB,OPB,FSL PLB,OPB,FSL Can have multiple masters (e.g. processors) Can have multiple masters (e.g. processors) Scale well for current uses of FPGAs Scale well for current uses of FPGAs Existing NoCs Existing NoCs Research projects Research projects Proprietary projects Proprietary projects Application specific (streaming…) Application specific (streaming…) Not built for parameterization, some other VALID focus Not built for parameterization, some other VALID focus

NoCem Specification Synthesizable VHDL Synthesizable VHDL Heavy use of generics / generate statements Heavy use of generics / generate statements Requires minimal Xilinx IP (FIFOs…) Requires minimal Xilinx IP (FIFOs…) To modify anything To modify anything Change generics, everything automatically generated Change generics, everything automatically generated E.g. to go from 2x2 mesh with 16b datawidth to 4x4 torus with 8b datawidth, change 3 lines of code! E.g. to go from 2x2 mesh with 16b datawidth to 4x4 torus with 8b datawidth, change 3 lines of code!

NoCem Interface FIFO-ish FIFO-ish Enqueue and dequeue path for every access point Enqueue and dequeue path for every access point Packet Control and Data paths Packet Control and Data paths Meaning of those paths depends on NoC configuration Meaning of those paths depends on NoC configuration Datapath Datapath Only variable width. Length of packet determined by packet control Only variable width. Length of packet determined by packet control Packet control: src, dest, packet length Packet control: src, dest, packet length Underlying Network reads toplevel packet structure, reads correct fields at correct times Underlying Network reads toplevel packet structure, reads correct fields at correct times

NoCem Bridges Use Existing Buses, bridge to NoC Use Existing Buses, bridge to NoC Integration into existing Xilinx tool flows Integration into existing Xilinx tool flows NoC can look like memory, SoC, … NoC can look like memory, SoC, … Use IPIF interface Use IPIF interface PLB, OPB PLB, OPB Different bus widths… Different bus widths… But processors both 32b But processors both 32b

How Big is NoCem? NoC Dimensions DatawidthLUTs xc2vp30 LUTs used 2x216b4,08614% 3x316b11,69342% 4x416b21,57078% 2x232b5,82221% 3x332b16,39459% 4x432b34,370125% Mesh, 16-deep channel FIFOs, RR Arbitration

Example Uses Memory Architecture (in paper) Memory Architecture (in paper) Various distributed cache configurations Various distributed cache configurations Asymmetric Processor Configuration Asymmetric Processor Configuration Using Microblaze, PowerPC Using Microblaze, PowerPC Special Processor Offloads Special Processor Offloads Floating Point, Network Processing Floating Point, Network Processing All can be emulated over NoC using NoCem…

For Release We want NoCem to be used! We want NoCem to be used! Already in use at CU Boulder Already in use at CU Boulder Full source will be made available online Full source will be made available online To do for release To do for release Clean/zip up code Clean/zip up code Some Documentation Some Documentation ETA: April 2006 ETA: April 2006

Conclusions NoCem as a research tool NoCem as a research tool Open source Open source Non-proprietary Non-proprietary Non application Specific Non application Specific NoCem for multicore processor research NoCem for multicore processor research Allows NoC exploration Allows NoC exploration Easy integration into Xilinx EDK flow Easy integration into Xilinx EDK flow Useful for a variety of research topics in this space Useful for a variety of research topics in this space

Any Questions?