ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL.

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Presentation transcript:

ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL

Part 1: Introduction to Lab 2 Implementing Combinational Logic in VHDL. Part 2: Example: miniALU. Part 3: Variable Rotator. Part 4: Hands-on Session: Simulation Using ISim and ModelSim. Part 5: Demos of Lab 1. Agenda for today

Part 1 Introduction to Lab 1 Implementing Combinational Logic in VHDL

Interface of ALU

Table of Operations

Block Diagram

Part 2 Example: Mini ALU Example of a Problem Similar to Task 1

opcode A B M R Mini ALU

MnemonicOperationOpcode ADDABR= A + B0000 ADDAMR = A + M0001 SUBABR = A - B0010 SUBAMR = A - M0011 NOTAR = NOT A0100 NOTBR = NOT B0101 NOTMR = NOT M0110 ANDABR = A AND B0111 ANDAMR = A AND M1000 ORABR = A OR B1001 ORAMR = A OR M1010 XORABR = A XOR B1011 XORAMR = A XOR M1100

Block diagram

Part 3 Variable Rotator Example of a Problem Similar to Bonus Task

Function C = A <<< B A – 4-bit data input B – 2-bit rotation amount

Interface A B C

Block diagram C

Fixed Rotation in VHDL A(3) A(2) A(1) A(0) A(2)A(1)A(0)A(3) A<<<1 SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); ArotL <= A(2 downto 0) & A(3); ArotL A

Part 4 Hands-on Session Simulation Using ISim and ModelSim