Low Power SRAM VLSI Final Presentation Stephen Durant Ryan Kruba Matt Restivo Voravit Vorapitat

High Level Architecture SRAM Block 5:32 Block Enable ADDR OUT

Block I/O SRAM Block READ WRITE ADDR DATA BLK ENABLE OUT

Output Buffering SRAM Block Sense Amp ADDR 13:12 Out ADDR 14 BLK_EN0 2:4 Decode r BLK_EN1 BLK_EN2 BLK_EN3

SRAM Block Precharge SASA Write Decode r 6:64 Pulse Gen 1 Pulse Gen 2 ADDR Dela y Pulse Gen 1 BLK_EN CLK Block Level Architecture SASA SASA SASA BLK_EN

Input Gating SRAM Block x8 Buffer ADDR 14:13 Register READ WRITE ADDR DATA

Word Line Pulse Pulse WL to reduce the drop in bit line voltage during a read Size the inverters to create min WL pulse length min WL pulse occurs before the point where the sense amp can no longer execute a read

Sense Amp Enabling Sense amp enabled after WL pulse to maximize differential current  Wordline pulse generator clocks a second pulse generator to ensure proper SA timing SAE signal and precharge signal separate to allow outputs to hold to end of clock cycle

Sense Amp Size the three nmos transistors to control:  Bit line voltage drop  Delay

Gate Length Vs. Bit Line Voltage Drop Using a 5 V vdd and allowing OutB to drop to 4 V min

Delay from SAE to Out From 50% SAE high to 50% Out low Same parameters as bit line voltage graph

Memory Partitioning 32 blocks *256 rows *128 columns  balance between idle block power savings and peripheral circuitry  resulting block aspect ratio relatively square to limit maximum WL/BL capacitances  WL partitioning and four words/row to reduce power

Simulation Model Multiple voltage sources to accurately measure energy  Wordline, active column, inactive column, and peripheral Etotal = E WL +32E act +96E inact + E peripheral

Low Power Techniques

Optimal Signal Order for Energy Goal: Making WL pulse as short as possible. Read SAE must be asserted only after WL pulse ends. Write WL pulse must start after BL or BLB completely discharged.

WL BL CL K SA E Write ’0’Write ’1’ Read

Lower Vdd Energy=C eff V dd 2 (Rail to Rail) -Expected quadratic energy reduction Energy=C eff V dd ∆V(BL/BLB during read) - ∆V should scale down but may not be as fast as V dd so we expect between linear and quadratic energy reduction.

Simulation Result for 1 bit Note: The Read/Write/Dread shown here is BL energy only

How far should we go?

Clock Gating Try to reduce the capacitance that high activity signal have to drive. Example: WL Pulse which have to drive 256 of 2-input NAND!

EffLoad=256EffLoad=128+2 Level 0 Level 1

Even Further EffLoad=64+4 Level 2

Simulation Result

Some note about clock gating It act like a decoder, in our design we choose to use level 2 clock gating for WL pulse so we did not need 8 to 256 decode any more, we just need the 6 to 64.