1 VHDL & Verilog Simulator. Modelsim. 2 Change the directory to where your files exist (All of the files must be in a same folder). Modelsim.

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Presentation transcript:

1 VHDL & Verilog Simulator. Modelsim

2 Change the directory to where your files exist (All of the files must be in a same folder). Modelsim

3 Create a work library for your design which contains design compile information. Modelsim

4 Create the library through this dialog box. Modelsim

5 You can see all information about your design by selecting All item from View menu. Modelsim

6 Modelsim

7 First, compile your source files. Modelsim

8 Choose what file should be compiled. Modelsim

9 After successful compilation, load your design. Modelsim

10 Select the design’s top-level module (i.e. test bench) to be loaded. Modelsim

11 Modelsim After successful loading…

12 Modelsim Add signals in the module’s region to the waveform analyzer.

13 Modelsim Run the simulator to simulate the described circuit.

14 Modelsim See and verify your simulation results.

15 Modelsim You can change the radix of the waveforms.

16 Modelsim Also, You can change the color of waveforms.