MICAS Department of Electrical Engineering (ESAT) Update of the “Digital EMC project” May 9th, 2006 AID–EMC: Low Emission Digital Circuit Design Junfeng.

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Presentation transcript:

MICAS Department of Electrical Engineering (ESAT) Update of the “Digital EMC project” May 9th, 2006 AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS

MICAS Department of Electrical Engineering (ESAT) Outline 1. Theoretical analysis of the EMI regulator 2. Future work

MICAS Department of Electrical Engineering (ESAT) Why we need small signal analysis Frequency H(s)-dB peaking

MICAS Department of Electrical Engineering (ESAT)  z1 – G m /C aux  z2 – parasitic zero, high frequency  p1 – Pole at V ctrl : G m /C aux  p2 – Pole at V VDD_input : g m /C tank  p3 – pole caused by compensation path, high frequency Current TF: small signal model

MICAS Department of Electrical Engineering (ESAT)  z1 cancel off the  p1 Make the  p2 cut-off frequency This zero is intrinsic for this feedback topology sacrifices dynamic noise performance Make  p2 dominant Advanced compensation techniques needed Current TF: pole-zero tracking Frequency H(s)-dB  z1  p1  p2 peaking Options

MICAS Department of Electrical Engineering (ESAT) Current TF: pole-zero tracking Frequency |H(s)|-dB  z1  p1  p2 peaking

MICAS Department of Electrical Engineering (ESAT) Key Idea : Achieving Stability Without Sacrificing Dynamic Supply Current Rejection R-C compensation no miller effect now ! R C added for moving the output pole high frequency, also for improvement of the dynamic di/dt rejection Reduced Gm of OTA Possible solution

MICAS Department of Electrical Engineering (ESAT) Stability analysis  p1 – Pole at V ctrl : [r ota C aux ] -1  p2 – Pole at V VDD_input : [(r o ||r c )C tank ] -1  z1 – [r aux C aux ] -1 p2 p1 z1

MICAS Department of Electrical Engineering (ESAT) Stability--Simulation results C tank : 100p I load : 25uA~72m A G m : 4uA/V R C : 1K C tank : 100p C aux : 20p F R aux : 100 K φ> 72 °

MICAS Department of Electrical Engineering (ESAT) Current TF analysis  p1 –  p2 –  z1 –  z2 – high frequency R c makes  p1 and  z1 well separated

MICAS Department of Electrical Engineering (ESAT) Current TF--Simulation results C tank : 100p I load : 20uA~72m A G m : 4uA/V R C : 1K C tank : 100p C aux : 20p F R aux : 100 K 40mA 40uA 225uA 1.265mA TF vs. I Load 7.113mA -3dB AC behavior of the LOAD ?

MICAS Department of Electrical Engineering (ESAT) Current TF--Simulation results C tank : 100p C aux = 20pF~120pF I load : 1.256mA G m : 4uA/V R C : 1K C tank : 100p R aux : 100 K 0pF 120pF 40pF TF vs. C aux 80pF -3dB AC behavior of the LOAD ?

MICAS Department of Electrical Engineering (ESAT) “ Impedance” information ? EMI Regulator LDO / Series Regulator IC switching Z VDD_input Z V3v3 impedance EMI regulator should be designed to make dynamic adjustment according to the impedance changes of the LOAD

MICAS Department of Electrical Engineering (ESAT) Future work 1. Measurement and characterization of EMI regulator, EMI(di/dt) characterization of different circuits as a function of gate count, clock frequency,… Improved structure of EMI regulator for better dynamic noise suppression, 2. Continue research on the Clock strategy ? Need discussion later

MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention

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