Systems Architecture, Fourth Edition 1 Processor Technology and Architecture Chapter 4

2Systems Architecture, Fourth Edition Chapter Topics

3Systems Architecture, Fourth Edition CPU Operation

4Systems Architecture, Fourth Edition CPU Operation Actions performed by the CPU: Fetch cycle – data inputs are prepared for transportation into data groups. Fetch cycle – data inputs are prepared for transportation into data groups. Execution cycle – the transformation takes place and data output is stored. Execution cycle – the transformation takes place and data output is stored.

5Systems Architecture, Fourth Edition CPU Operation

6Systems Architecture, Fourth Edition Instructions and Instruction Sets Instruction – a command to the CPU to perform one of its primitive processing functions. Op Code – the unique binary number of the instruction. Operand – groups of bits that hold the input values for the instruction.

7Systems Architecture, Fourth Edition Instructions and Instruction Sets

8Systems Architecture, Fourth Edition Instructions and Instruction Sets

9Systems Architecture, Fourth Edition Instructions and Instruction Sets The NOT instruction transforms the boolean value true into false and the value false into true. NOT 0 = 1 NOT 0 = 1 NOT 1 = 0 NOT 1 = 0

10Systems Architecture, Fourth Edition Instructions and Instruction Sets The AND instruction generates the result true if both of its data inputs are true. 0 AND 0 = 0 1 AND 0 = 0 1 AND 0 = 0 0 AND 1 = 0 1 AND 1 = 1

11Systems Architecture, Fourth Edition Instructions and Instruction Sets The Inclusive OR instruction generates the value true if either or both data inputs are true. 0 OR 0 = 0 1 OR 0 = 1 0 OR 1 = 1 1 OR 1 = 1

12Systems Architecture, Fourth Edition The Exclusive OR Instruction (XOR) generates the value true if either, but not both, data inputs are true. 0 XOR 0 = 0 1 XOR 0 = 1 0 XOR 1 = 1 1 XOR 1 = 0 Instructions and Instruction Sets

13Systems Architecture, Fourth Edition The ADD instruction accepts two numeric inputs and produces their arithmetic sum = = = = 10 Instructions and Instruction Sets

14Systems Architecture, Fourth Edition The Shift instruction moves bit strings to the left or the right. Instructions and Instruction Sets

15Systems Architecture, Fourth Edition The Logical Shift instruction is typically used to extract a single bit from a bit string. Instructions and Instruction Sets

16Systems Architecture, Fourth Edition The Arithmetic Shift instruction performs multiplication or division. Shift OperationBinary ValueDecimal Value No shift (original number) Shift left by 2 bits Shift right by 2 bits Multiplication – shifting one bit to the left, multiplies the value by 2. Division – shifting one bit to the right, divides the value by 2. Instructions and Instruction Sets

17Systems Architecture, Fourth Edition Instructions and Instruction Sets

18Systems Architecture, Fourth Edition Sequence Control Instructions: Unconditional Branch Unconditional Branch Conditional Branch Conditional Branch Halt Halt Instructions and Instruction Sets

19Systems Architecture, Fourth Edition The Unconditional Branch causes the processor to always depart from the normal sequence. The Unconditional Branch causes the processor to always depart from the normal sequence. The Conditional Branch occurs only if a specified condition is met. The Conditional Branch occurs only if a specified condition is met. The Halt instruction suspends the normal flow of instruction execution. The Halt instruction suspends the normal flow of instruction execution. Instructions and Instruction Sets

20Systems Architecture, Fourth Edition Instructions and Instruction Sets

21Systems Architecture, Fourth Edition Instructions and Instruction Sets

22Systems Architecture, Fourth Edition Instruction Format An instruction format is a template that specifies the number of operands and the position and length of the op code and operands.

23Systems Architecture, Fourth Edition Instruction Format

24Systems Architecture, Fourth Edition Instruction Format Fixed instruction length – simplify the instruction-fetching processes implemented with the control unit. Fixed instruction length – simplify the instruction-fetching processes implemented with the control unit. Variable instruction length – the amount by which the instruction pointer is incremented after the fetch is the length of the most recently fetched instruction. Variable instruction length – the amount by which the instruction pointer is incremented after the fetch is the length of the most recently fetched instruction.

25Systems Architecture, Fourth Edition Clock Rate Clock Rate – the frequency at which the system clock generates timing pulses. Clock Rate – the frequency at which the system clock generates timing pulses. The rate are measured in Hertz (Hz) – one cycle per second. The rate are measured in Hertz (Hz) – one cycle per second.

26Systems Architecture, Fourth Edition CPU Registers General-purpose – used to hold intermediate results or frequently used values in the currently executing programs. General-purpose – used to hold intermediate results or frequently used values in the currently executing programs. Special-purpose Special-purpose Instruction register Instruction register Instruction pointer Instruction pointer Program status word Program status word

27Systems Architecture, Fourth Edition Word Size Word – unit of data that contains a fixed number of bytes or bits. The amount of data that a CPU processes at one time. Word – unit of data that contains a fixed number of bytes or bits. The amount of data that a CPU processes at one time. Relationship between word size and CPU speed. Relationship between word size and CPU speed.

28Systems Architecture, Fourth Edition Word Size

29Systems Architecture, Fourth Edition The Physical CPU Switches and Gates: the basic building blocks of computer processing circuits are electrical gates. Switches and Gates: the basic building blocks of computer processing circuits are electrical gates. Basic processing functions on binary digits are performed with the logical functions: (AND, OR, XOR, and NOT) Basic processing functions on binary digits are performed with the logical functions: (AND, OR, XOR, and NOT)

30Systems Architecture, Fourth Edition The Physical CPU

31Systems Architecture, Fourth Edition The Physical CPU More complex processing functions require more complicated arrangements of gates. More complex processing functions require more complicated arrangements of gates. A full-adder and half-address can be formed using the basic gates. A full-adder and half-address can be formed using the basic gates.

32Systems Architecture, Fourth Edition The Physical CPU

33Systems Architecture, Fourth Edition The Physical CPU Heat – the negative effects of heat on electrical conductivity are damage to the conductor and changes in the inherent resistance of the conductor. Heat Sink – an object specifically designed to absorb heat and rapidly dissipate it using air or water movement.

34Systems Architecture, Fourth Edition The Physical CPU

35Systems Architecture, Fourth Edition The Physical CPU Processor Fabrication: Transistors and Integrated Circuits – transistors are made of semiconductor material that has been treated with chemical impurities to enhance the semiconducting effects. Transistors and Integrated Circuits – transistors are made of semiconductor material that has been treated with chemical impurities to enhance the semiconducting effects. Integrated Circuit – implements several transistors and their interconnections on a single chip. Integrated Circuit – implements several transistors and their interconnections on a single chip.

36Systems Architecture, Fourth Edition The Physical CPU Microchips and Microprocessors A microprocessor is a microchip that contains all of the circuits and connections that implement a CPU.

37Systems Architecture, Fourth Edition The Physical CPU Moore’s Law – observed that the rate of increase in transistor density on microchips had increased steadily, roughly doubling every 18 to 24 months.

38Systems Architecture, Fourth Edition

39Systems Architecture, Fourth Edition Year of IntroductionTransistors , , , , ,000 Intel386™ processor ,000 Intel486™ processor19891,180,000 Intel® Pentium® processor19933,100,000 Intel® Pentium® II processor19977,500,000 Intel® Pentium® III processor199924,000,000 Intel® Pentium® 4 processor200042,000,000 Intel® Itanium® processor ,000,000 Intel® Itanium® 2 processor ,000,000

40Systems Architecture, Fourth Edition The Physical CPU

41Systems Architecture, Fourth Edition The Physical CPU

42Systems Architecture, Fourth Edition The Physical CPU

43Systems Architecture, Fourth Edition Future Trends Optical Processing Optical Processing Electro-Optical Processing Electro-Optical Processing Quantum Processing Quantum Processing

44Systems Architecture, Fourth Edition Future Trends Optical Processing: Could eliminate interconnection and simplify fabrication problems. Could eliminate interconnection and simplify fabrication problems. It is possible to connect fiber optic devices without wires. It is possible to connect fiber optic devices without wires.

45Systems Architecture, Fourth Edition Future Trends Electro-Optical Processing: Can become the interface between semiconductor processors and purely optical memory and storage devices. Can become the interface between semiconductor processors and purely optical memory and storage devices. Can be used to fabricate conventional semiconductors. Can be used to fabricate conventional semiconductors.

46Systems Architecture, Fourth Edition Future Trends Quantum Processing: Uses quantum states to simultaneously encode two bits, called a qubit. Uses quantum states to simultaneously encode two bits, called a qubit. Uses quantum processing devices to perform computations. Uses quantum processing devices to perform computations.

47Systems Architecture, Fourth Edition Assign #6 Assign #6 Read chapter 6, pg. 238, review questions 1, 2, 4, 5, 9, 10; pg. 241, research problem 1 - 1/2 page summary. Read chapter 6, pg. 238, review questions 1, 2, 4, 5, 9, 10; pg. 241, research problem 1 - 1/2 page summary. Midterm Midterm October 27 October 27