Lecture #27 Page 1 ECE 4110–5110 Digital System Design Lecture #27 Agenda 1.Counters Announcements 1.Finish reading Wakerly sections 8.1, 8.2, 8.4, 8.5 (Sequential timing, registers, counters, shift registers). Skip the AHDL and Verilog sections 8.2.6, 8.2.8, 8.4.5, 8.4.7, 8.5.7, 8.5.9

Lecture #27 Page 2 Counters Counters - special name of any clocked sequential circuit whose state diagram is a circle - there are many types of counters, each suited for particular applications

Lecture #27 Page 3 Counters Binary Counter - state machine that produces a straight binary count - for n-flip-flops, 2 n counts can be produced - the Next State Logic "F" is a combinational SOP/POS circuit - the speed will be limited by the Setup/Hold and Combinational Delay of "F" - this gives the maximum number of counts for n-flip flops

Lecture #27 Page 4 Counters Toggle Flop - a D-Flip-Flop can produce a "Divide-by-2" effect by feeding back Qn to D - this topology is also called a "Toggle Flop“ or TFF

Lecture #27 Page 5 Counters Ripple Counter - Cascaded TFF can be used to form rippled counter - there is no Next State Logic - this is slower than a straight binary counter due to waiting for the "ripple" - this is good for low power, low speed applications

Lecture #27 Page 6 Counters Synchronous Counter with ENABLE - an enable can be included in a "Synchronous" binary counter using TFF with EN - the enabled is implemented by AND'ing the Q output prior to the next toggle flop - this gives us the "ripple" effect, but also gives the ability to run synchronously - a little faster than ripple counter, and has less gates than a straight binary counter circuit

Lecture #27 Page 7 Counters Shift Register-based –Shift register is a chain of D-Flip- Flops that pass data to one another Good for Serial-to-Parallel conversion. How? For n-flip-flops, the data is present at the final state after n clocks

Lecture #27 Page 8 Counters Ring Counter - Shift register based –feeding the output of a shift register back to the input creates a "ring counter“ –also called a "One Hot“ –The first flip-flop needs to reset to 1, while the others reset to 0 –for n flip-flops, there will be n counts

Lecture #27 Page 9 Counters Johnson Counter - Also, shift reg based. -Feeds the inverted output of a shift register back to the input creates a "Johnson Counter" - this gives more states with the same reduced gate count - all flip-flops can reset to 0 - for n flip-flops, there will be 2n counts

Lecture #27 Page 10 Counters Linear Feedback Shift Register (LFSR) Counter - Shift register based, as named -all of the counters based off of shift registers give far less states than the 2 n counts that are possible - a LFSR counter is based off of the theory of finite fields - created by French Mathematician Evariste Galois ( ) - for each size of shift register, a feedback equation is given which is the sum modulo 2 of a certain set of output bits - this equation produces the input to the shift register - this type of counter can produce 2 n -1 counts, nearly the maximum possible

Lecture #27 Page 11 Counters Linear Feedback Shift Register (LFSR) Counter - the feedback equations are listed in Table 8.26 of the textbook - It is defined that bits always shift from X n-1 to X 0 (or Q 0 to Q n-1 ) as we defined the shift register previously - they each use XOR gates (sum modulo 2) of particular bits in the register chain ex) nFeedback Equation 2X2 = X1  X0 3X3 = X1  X0 4X4 = X1  X0 5X5 = X2  X0 6X6 = X1  X0 7X7 = X3  X0 8X8 = X4  X3  X2  X0 : : : :

Lecture #27 Page 12 Counters Linear Feedback Shift Register (LFSR) Counter ex) 4-flip-flop LFSR Counter Feedback Equation = X1  X0 (or Q2  Q3 as we defined it) #Q(0:3) Sin this is 2 n -1 unique counts repeat 1000