EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process -II Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE4271 VLSI Design

EE141 © Digital Integrated Circuits 2nd Manufacturing 2 2 Challenge Illumination source Mask Objective Lens Aperture Wafer 193nm 45nm

EE141 © Digital Integrated Circuits 2nd Manufacturing 3 3 Mask v.s. Printing 0.25µ0.18µ 0.13µ 90-nm65-nm Layout What you design is NOT what you get!

EE141 © Digital Integrated Circuits 2nd Manufacturing 4 Motivation  Chip design cannot be fabricated  Gap –Lithography technology: 193nm wavelength –VLSI technology: 45nm features  Lithography induced variations –Impact on timing and power l Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported. Technology node 130nm90nm65nm45nm Gate length (nm) Tolerable variation (nm) Wavelength (nm)

EE141 © Digital Integrated Circuits 2nd Manufacturing 5 5 Gap: Lithography Tech. v.s. VLSI Tech. 193nm 28nm, tolerable distortion: 2nm Increasing gap  Printability problem (and thus variations) more severe!

EE141 © Digital Integrated Circuits 2nd Manufacturing 6 Design Rules

EE141 © Digital Integrated Circuits 2nd Manufacturing 7 Design Rules  Interface between designer and process engineer  Guidelines for constructing process masks  Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

EE141 © Digital Integrated Circuits 2nd Manufacturing 8 Lambda Rule  Every distance in layout rules is specified by lambda  Given a process, lambda is set to a specific value.  Process technology is defined using minimum line width. 0.25um technology means minimum line width is 0.25um. Lambda=minimum line width/2.  For a 0.25um process, lambda=0.125um  In practice, scaling is often not linear.  Industry usually uses micron rule and lambda rule is used only for prediction/estimation of the impact of technology scaling to a design.

EE141 © Digital Integrated Circuits 2nd Manufacturing 9 Layers in 0.25  m CMOS process

EE141 © Digital Integrated Circuits 2nd Manufacturing 10 Intra-Layer Design Rules Metal2 4 3 Rules are used to mitigate fabrication error

EE141 © Digital Integrated Circuits 2nd Manufacturing 11 Transistor Layout

EE141 © Digital Integrated Circuits 2nd Manufacturing 12 Layout Editor

EE141 © Digital Integrated Circuits 2nd Manufacturing 13 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

EE141 © Digital Integrated Circuits 2nd Manufacturing 14 Some Packages

EE141 © Digital Integrated Circuits 2nd Manufacturing 15 Wire Bonding (not printed) Bond wire

EE141 © Digital Integrated Circuits 2nd Manufacturing 16 Imprinted Tape-Automated Bonding Disadvantage: Must place I/O pins at the specific locations (i.e., around the boundary on the die).

EE141 © Digital Integrated Circuits 2nd Manufacturing 17 Flip-Chip Bonding  Flip-Chip places connection across the chip rather than around boundary.  The bond wire is replaced with solder bump balls directly placed on the die surface  Chip is flipped upside down  Carefully align to package  Heat to melt solder bump balls