1 Homework #5 A bit error rate tester (BERT) Chris Allen Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm.

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Presentation transcript:

1 Homework #5 A bit error rate tester (BERT) Chris Allen Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm

2 A bit error rate tester (BERT) A Bit Error Rate Tester (BERT), also known as Bit Error Ratio Tester is an electronic test instrument used to test a component or system’s signal transmission fidelity. Using a sequence of logical ones and zeros generated by a pseudo- random binary sequencer, a BERT compares the received signals against the know binary sequence to detect bit errors. The main building blocks of a Bit Error Rate Tester are: Pattern Generator, which transmits a defined test pattern to the DUT or test system Error Detector connected to the DUT or test system, to count the errors generated by the DUT or test system Clock signal generator to synchronize the pattern generator and the error detector

3 A bit error rate tester (BERT) Design shows implementation using GigaBit Logic components Assignment requires use of Synergy/Micrel ECL components Assignment involves Schematic Board stackup Layout Timing analysis, max clock freq Supply current analysis Bill of materials Cooling analysis