BR 8/99 Arithmetic Operations We will review the arithmetic building blocks we have previously used, and look at some new ones. –Addition –incrementer.

Slides:



Advertisements
Similar presentations
Modular Combinational Logic
Advertisements

1 ECE 4436ECE 5367 Computer Arithmetic I-II. 2 ECE 4436ECE 5367 Addition concepts 1 bit adder –2 inputs for the operands. –Third input – carry in from.
ECE2030 Introduction to Computer Engineering Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers Prof. Hsien-Hsin Sean Lee School.
Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going.
1 Lecture 12: Hardware for Arithmetic Today’s topics:  Designing an ALU  Carry-lookahead adder Reminder: Assignment 5 will be posted in a couple of days.
n-bit comparator using 1-bit comparator
Comparator.
Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University Arithmetic See: P&H Chapter 3.1-3, C.5-6.
ECE 331 – Digital System Design
1 CS 140 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris.
1 Comparators Discussion D A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin =
ECE C03 Lecture 61 Lecture 6 Arithmetic Logic Circuits Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
30 September 2004Comp 120 Fall September 2004 Chapter 4 – Logic Gates Read in Chapter 4 pages , , section 4.8 through top of page.
Arithmetic-Logic Units CPSC 321 Computer Architecture Andreas Klappenecker.
Overview Iterative combinational circuits Binary adders
ECE 301 – Digital Electronics
ECE 301 – Digital Electronics
1 Comparators: Procedures Discussion D9.2 Example 22.
Chapter 5 Arithmetic Logic Functions. Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR,
Calculator Lab Overview Note: Slides Updated 10/8/12
Digital Electronics.
Digital Arithmetic and Arithmetic Circuits
Chapter 4 – Arithmetic Functions and HDLs Logic and Computer Design Fundamentals.
Fall 2004EE 3563 Digital Systems Design EE 3563 Comparators  Comparators determine if two binary inputs are equal  Some will signal greater than/less.
Chapter 6-1 ALU, Adder and Subtractor
L26 – Datapath ALU implementation
Logic Gates Logic gates are electronic digital circuit perform logic functions. Commonly expected logic functions are already having the corresponding.
Basic Addition Review Basic Adders and the Carry Problem
درس مدارهای منطقی دانشگاه قم مدارهای منطقی محاسباتی تهیه شده توسط حسین امیرخانی مبتنی بر اسلایدهای درس مدارهای منطقی دانشگاه.
Arithmetic Functions BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors,
Half Adder & Full Adder Patrick Marshall. Intro Adding binary digits Half adder Full adder Parallel adder (ripple carry) Arithmetic overflow.
1 Arithmetic I Instructor: Mozafar Bag-Mohammadi Ilam University.
BR 8/991 Combinational Building Blocks 2/1 Multiplexor (MUX) I0 I1 Y S if S = 0, then Y = I0 if S = 1, then Y = I1 Y = I0 S’ + I1 S I0 I1 Y S A[3:0] B[3:0]
Topics covered: Arithmetic CSE243: Introduction to Computer Architecture and Hardware/Software Interface.
ECE 331 – Digital System Design Multi-bit Adder Circuits, Adder/Subtractor Circuit, and Multiplier Circuit (Lecture #12)
1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.
CS 151: Digital Design Chapter 4: Arithmetic Functions and Circuits
CHAPTER 2 Digital Combinational Logic/Arithmetic Circuits
ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill.
Arithmetic-Logic Units. Logic Gates AND gate OR gate NOT gate.
1 Lecture 14 Binary Adders and Subtractors. 2 Overview °Addition and subtraction of binary data is fundamental Need to determine hardware implementation.
1 Lecture 11: Hardware for Arithmetic Today’s topics:  Logic for common operations  Designing an ALU  Carry-lookahead adder.
Lecture #23: Arithmetic Circuits-1 Arithmetic Circuits (Part I) Randy H. Katz University of California, Berkeley Fall 2005.
ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Adders,subtractors, ALUs.
Basic Addition Review Basic Adders and the Carry Problem Carry Propagation Speedup Speed/Cost Tradeoffs Two-operand Versus Multi-operand Adders.
UNIT 8 COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES
ETE 204 – Digital Electronics Combinational Logic Design Single-bit and Multiple-bit Adder Circuits [Lecture: 9] Instructor: Sajib Roy Lecturer, ETE,ULAB.
1 Computer Architecture & Assembly Language Spring 2009 Dr. Richard Spillman Lecture 11 – ALU Design.
Combinational logic circuit
Computer Arthmetic Chapter Four P&H.
Lecture Adders Half adder.
Swamynathan.S.M AP/ECE/SNSCT
Comparators Discussion DS-3.1.
FUNCTION OF COMBINATIONAL LOGIC CIRCUIT
ECE/CS 552: Arithmetic and Logic
ECE 331 – Digital System Design
CSE Winter 2001 – Arithmetic Unit - 1
King Fahd University of Petroleum and Minerals
Arithmetic Circuits (Part I) Randy H
Lecture 11: Hardware for Arithmetic
Digital Systems Section 12 Binary Adders. Digital Systems Section 12 Binary Adders.
CS 140 Lecture 14 Standard Combinational Modules
Chapter 5 – Number Representation and Arithmetic Circuits
Homework Reading Machine Projects Labs
Overview Part 1 – Design Procedure Part 2 – Combinational Logic
CSE 140 Lecture 14 Standard Combinational Modules
Instructor: Mozafar Bag-Mohammadi University of Ilam
ECE 352 Digital System Fundamentals
Number Representation
Presentation transcript:

BR 8/99 Arithmetic Operations We will review the arithmetic building blocks we have previously used, and look at some new ones. –Addition –incrementer –Addition/subtraction –decrementer –Comparison

BR 8/99 Binary Adder F (A,B,C) = A xor B xor C G = AB + AC + BC These equations look familiar. These define a Binary Full Adder : AB S CiCo Cin AB Cout Sum Sum = A xor B xor Cin Cout = AB + Cin A + Cin B = AB + Cin (A + B) Full Adder (FA)

BR 8/99 4 Bit Ripple Carry Adder AB S CiCo AB S CiCo AB S CiCo AB S CiCo Cin A(0) Cout B(0)A(1)B(1)A(2)B(2)A(3)B(3) C(0)C(1)C(2)C(3)C(4) Sum(0)Sum(1)Sum(2)Sum(3) A[3:0] B[3:0] SUM[3:0] +

BR 8/99 Incrementer A(0) A(1)A(2)A(3) EN Y(0)Y(1)Y(2) Y(3) A[3:0] EN Y[3:0] inc If EN = 1 then Y = A + 1 If EN = 0 then Y = A xor

BR 8/99 How did we get the Incrementer equations? Full Adder equations: Sum = A xor B xor Cin Cout = AB or Cin A or Cin B = AB or Cin (A or B) Let B = 0, Cin = 1 so that Sum = A + 1. Then equations simplify to: SUM = A xor 1 xor 0 = A xor 1 = A’ Cout = 0 or 1 (A or 0) = A. If we want an “En” input, then we want SUM = A if En=0, else SUM = A+1 if En = ‘1’. Filling in the above equations: SUM = A En’ or A’ En = A xor En Cout = A En (note that Cout = 0 if En = 0). The “Cout” of one bit becomes the “En” signal for the next bit!!!!

BR 8/99 A Subtractor What is subtraction? A - B = A + (-B) How do you take the negative of a number? Depends on the sign representation (signed magnitude, 1s complement, 2s complement). Lets assume 2’s complement since it is most common). (-B) = B’ + 1 So: A - B = A + (-B) = A + B’ + 1

BR 8/99 Subtractor using an Adder A[3:0] B[3:0] SUM[3:0] = A - B + B’[3:0] Cin 1 What if we want a block that can do both addition and subtraction?

BR 8/99 Adder/Subtractor A[3:0] B[3:0] + Cin Sub 0 1 Y[3:0] VHDL representation: Y <= (A-B) when (Sub = ‘1’) else A+B; 2/1 Mux

BR 8/99 Recall what a Comparator is... Equality comparator. A AeqB B N N A=B if A(0) = B(0) and A(1) = B(1) … and A(n-1)=B(n-1) Recall that “xnor” function is ‘1’ if A=0, B=0 or A=1, B=1! So AeqB is: AeqB = (A(0) xnor B(0)) and (A(1) xnor B(1)) and ….etc.

BR 8/99 What is logic structure for equality comparator? A(N-1) xnor B(N-1)A(N-2)B(N-2)A0 xnor B0 AND Tree (will be multiple AND gates in tree arrangement) xnor AeqB

BR 8/99 Is there another Logic structure possible? If (A(0) = B(0) then if (A(1) = B(1) then …. If (A(N-1) = B(N-1) then AeqB = ‘1’; !!!!! Compare “iteratively” from LSB to MSB A(0)B(0)A(1)B(1)A(N-1)B(N-1) AeqB Signal from one bit block to next is “enable” for that block.

BR 8/99 Iterative Comparator Structure A(0) B(0) A(1)B(1)A(N-1)B(N-1) AeqB xnor An advantage to this structure is that the design for each bit is the same same, and we can extend it indefinitely. But it will be slow.

BR 8/99 Two ways to do a Large AND function A(0) A(1) A(2) A(N-1) Multi-level. # of levels depends on total number of inputs, number of inputs on each gate. A tree arrangment like this will take more gates, but will be fast. Serial arrangement. Will take less gates, but will be slow.

BR 8/99 What about “ ” (greater than?) Full comparator. A AltB AeqB B AgtB N N The logic for AltB, AgtB depends on whether we are comparing signed numbers or not. We will assume unsigned numbers for now.

BR 8/99 Logic for “AgtB” (unsigned) Consider A > B, both N bit numbers, A[N-1:0], B[N-1:0] If (A(N-1) = ‘1’ and (B(N-1) = ‘0’) then AgtB = ‘1’; elsif ((A(N-1) = B(N-1)) and (A(N-2) = ‘1’ and (B(N-2)=‘0’) ) then AgtB = ‘1’; etc... A=1xxx… B=0xxxxx A=01xx… B=00xxxx A=11xx… B=10xxxx Look at “bit(i)”. The enable signal from previous bit is A= B up until now. If this is ‘1’, then we need to do a comparison. However, if “AgtB” is already true, then we don’t need to do comparison and can skip this comparison!

BR 8/99 Iterative Implementation of AgtB En_i Skip_i En_o Skip_o En_i Skip_iSkip_o En_o A(i+1)B(i+1)A(i)B(i) en_o = (A xnor B) and en_i ; If (skip_i = ‘1’) then skip_o = ‘1’; else skip_o = en_i and (A and B’) ; end if; En_i Skip_i En_o Skip_o A(i-1)B(i-1) A=B signal

BR 8/99 Logic Implementation en_o = (A xnor B) and en_i; If (skip_i = ‘1’) then skip_o = ‘1’; else skip_o = en_i and (A and B’) ; end if; xnor A B en_o skip_o skip_i Can use a K-map to simplify this logic. The skip_o of the LAST bit is the AgtB signal! The en_o of the LAST bit is the AeqB signal! What about AltB??? AltB = AgtB’ and AeqB’ en_i

BR 8/99 Final Comparator En_i Skip_i Skip_o En_o B(N-1)A(N-1) 1 0 En_i Skip_i Skip_o En_o B(i)A(i) En_i Skip_i Skip_o En_o B(0)A(0) AeqB AgtB AltB <= not (AeqB) and not (AgtB);

BR 8/99 En(8) Skip(8) skip(7) En(7) A(7) 1 B(7) 0 skip(6) En(6) A(6)B(6) En(7) Skip(7) En(6) Skip(6) skip(5) En(5) A(5)B(5) skip(4) En(4) A(4)B(4) En(5) Skip(5) En(4) Skip(4) skip(3) En(3) A(3)B(3) skip(2) En(2) A(2)B(2) En(3) Skip(3) En(2) Skip(2) skip(1) En(1) A(1)B(1) skip(0) En(0) A(0)B(0) En(1) Skip(1) AeqB AgtB en(i) = (A(i) xnor B(i)) and en(i+1); If (skip(i+1) = ‘1’) then skip(i)= ‘1’; else skip(i) = en(i) and (A(i) and B’(i)) ; end if; For i’th bit: 8 Bit Comparator

BR 8/99 architecture a of comp is signal en, skip: std_logic_vector(8 downto 0); begin aeqb <= en(0); agtb <= skip(0); altb <= (not en(0)) and (not skip(0)); process (a,b) begin en(8) <= '1'; skip(8) <= '0'; for i in 7 downto 0 loop en(i) <= not (a(i) xor b(i)) and en(i+1); if (skip(i+1) = '1') then skip(i) <= '1'; else skip(i) <= en(i+1) and (a(i) and not b(i)); end if; end loop; end process; end a; VHDL architecture that implements comparator logic as shown on previous slides.

BR 8/99 Alternate VHDL specification architecture a of compa is begin aeqb <= '1' when (a = b) else '0'; agtb b) else '0'; altb <= '1' when (a < b) else '0'; end a; Synthesis tool will pick a logic implementation for implementation of ‘=‘, ‘>’, ‘<‘ based on user constraints such as propagation delay.

BR 8/99 A B AeqB AltB AgtB Glitches in synthesized logic. Ok as long as we are using FFs to latch result.