L4 BCC – 1 Sep 2011 F. Roncarolo, U. Raich L.Soby, J.Tan, C.Zamantzas, F. Lenardon, C.Vuitton, G-J.Focker

DESIGN  Completed for almost all instruments (most of TL devices == L4 monitors)  Basically all devices will be tested at 3 MeV test stand  Open issues –Number of devices and locations: need frozen layout Once done: details about interconnections –Profile monitor in dump line (see later slide) –BLM detector type (see later slide) –Equipment of TL with station for laser stripping R&D SCHEDULE / BUDGET  Present advancement/plans/budget for design, fabrication, cabling and installation under control  BI Linac 4 review (with reviewers panel) on October 18 th (tbc and announced in the next few days) F. Roncarolo, U. RaichL4 BCC - 01 Sep 20112

3F. Roncarolo, U. Raich 3 BTVs now replaced by 1 WS or SEM GRID (H+V) From Layout DB

L4 BCC - 01 Sep 20114F. Roncarolo, U. Raich  Copy of LEBT monitors –100 mm diameter –Up to 200 MHz sampling rate  Acquisition sync. with the distributor, to know how much beam current goes to each PSB ring –Electronics ready for such option –Need FPGA code update (likely not possible before LS1)  In general –Do we agree on the number of devices? –Foreseen by BI : 6, Layout DB: 7

 Shorted strip-line detectors –Same design for all L4 BPMs –Diameter for TL monitors: 100 mm, L = ~250mm –Electronics with down-mixing of 22 MHz  maximum sampling rate 4x22=88 MHz –50 ns pulse length beam position measurement foreseen by the design (noise levels to be investigated)  For TL: is # of monitors and location frozen ?  At the moment of installing TL BPMs: will it be possible to change the 17 old TL monitors (after BHZ20)? F. Roncarolo, U. RaichL4 BCC - 01 Sep J. Tan

 Same design as all L4 monitors – will require reduced pulse length (100us)  Mechanics ~ on schedule, 140 mm flange-to-flange (PIMs type)  New electronics under development, to be tested on 3 MeV test stand –200 kHz ADC band (5 us) –Wire polarization –New connectors and cables: 32 channels in 1 cable F. Roncarolo, U. RaichL4 BCC - 01 Sep Is this up to date? Once frozen: verify details of flange connections

 3 screens option abandoned  Additional monitor not included in BI plans –What are requirements? –SEM Grid or WS ?  Spare L4 SEM grid –single shot meas –24 wires fixed pitch  Spare L4 WS –multishot meas –40 um resolution (wire diam.)  SEM grid on stepping motor –Not foreseen by BI (can recuperate test bench device?) –Not single shot but can improve resolution with less shots than WS  new SEM with variable resolution (by variable rotation w.r.t. beam axis) –not foreseen  design new or try to recuperate L2 type device –When rotation != 90 deg: during single shot the sampling is done at different longitudinal locations F. Roncarolo, U. RaichL4 BCC - 01 Sep 20117

F. Roncarolo, U. RaichL4 BCC - 01 Sep W.Vigano, C. Zamantzas Auto-gain switching -Integrated detector signal sampled every 2 us -From pA to mA detector output current 2 us : sampling the integral  Electronics under development, in parallel to L4 linac and PSB new electronics  Special screened cables to minimize EM noise (problem in other world-wide linacs)  TL cable installation on stand-by while waiting for latest beam optics and BLM location s  Every second BLM location is equipped with a spare cable to host an additional monitor if needed  Choice of detector (Ionization chamber, chamber type, or possibly other detectors) under discussion Wide dynamic range expected !

 Aim at profile + emittance measurement  For Linac 4 –At least 1 station –Y dipole –Establish laser location and optical line path  If there will be no intermediate dump between 1st bend and BI line: –can test only laser stripping and profile meas (no emitt. meas) with a station after PIMS F. Roncarolo, U. RaichL4 BCC - 01 Sep LASER stripping H0 monitor Possible locations

 BCT – BPM –Low level completed or well on the way to completion –Need OP GUI development –All will be tested at 3 MeV test stand  SEM grids –Low level and OP GUI done, being used at test stand  BLM –Definition of the memory map CPU in readout simulation mode Start development of driver, RT software, etc. –First version of memory map (LINAC4) - end of September F. Roncarolo, U. RaichL4 BCC - 01 Sep

F. Roncarolo, U. RaichL4 BCC - 01 Sep

F. Roncarolo, U. RaichL4 BCC - 01 Sep

F. Roncarolo, U. RaichL4 BCC - 01 Sep